Can Recursive Bisection Alone Produce Routable Placements?
Supported by Cadence Can Can Recursive Recursive Bisection Bisection Alone Alone Produce Produce Routable Routable Placements? Placements? Andrew E. Caldwell Andrew B. Kahng Igor L. Markov http://vlsicad.cs.ucla.edu Outline Routability and the placement context Placement by recursive bisection UCLA Capo placer Empirical results Conclusions and open questions Routability is a Requirement For Placement VLSI placement is fixed-die, followed by routing Routing fails placement was not useful Algorithms that produce routable placements are more valuable (no fixes cleaner EDA) Timing-driven placement
does not excuse the routability requirement is a harder problem, not a different problem Question: can we achieve routability without increasing wirelength ? (via a better global placer) In This Work: WL-driven Placement Infeasible Given a circuit a [very good] black-box router Routing Definition a circuit placement is "100% auto-routable" the router automatically completes all nets without manual intervention OUR CRITERION: Less than 100% autoroutability == placement failure Sets the bar for placer evaluation Fixed-die vs Variable-die Fixed-die P&R (typically, N-layer metal)
cell sites and routing tracks are fixed cannot spread rows and insert routing tracks makes achieving routability much harder is implied by modern design techniques power/ground planning, hierarchical block methodology assumed by Cadence LEF/DEF formats assumed by most commercial EDA tools Variable-die P&R (typically, 2-layer metal) row geometries, utilization, area not known in advance
routability can be traded for area Routability Routability is not a purely 0-1 property router runtime explodes when routing gets harder May be harder with growing #nets need to use large benchmarks (10K cells and up) May be easier with increased # metal layers need to use very recent benchmarks Experimental question: Does decreasing overall WL improve routability and routed wirelength ? Recursive Bisection Placement etc. Recursive Bisection (RB) Placement Framework for leading commercial tools
fast and scalable can be extended to handle timing Key technologies balanced hypergraph bipartitioning UCLA MLPart (Caldwell/Kahng/Markov ASPDAC 2000) end-case processing optimal methods (Caldwell/Kahng/Markov ISPD `99) RB placement vastly improved in the last 2 years due to the multi-level partitioning breakthrough Experimental Q: does better RB improve routability? UCLA Capo Placement Tool Open-source: vlsicad.cs.ucla.edu, openeda.org Employs recent advances in recursive bisection This paper: nothing used beyond recursive bisection Improved flat Fiduccia-Mattheyses (FM) better performance for small partitioning tolerance VLSI Design 2000 Better Multi-Level Fiduccia-Mattheyses (MLFM) improves upon hMetis (DAC `97), faster ASP DAC 2000 New block splitting heuristics for vertical cuts
easier partitioning instances and increased solution space Hierarchical tolerance computation (UCLA TR-200002) Experimental Flow VLSI Circuit (LEF/DEF) Capo placer (Fast = 1/2 MLFM) Industry placer Legalization (~2sec) w/ industry placer Industry router from same vendor Computed: HPWL, WWL, routed WL and runtimes Test Cells Nets White #Metal case spaceLayers 1 + 11471 11828 24.30% 3
4 7 = 42352 44490 29.30% 5 Placer HPWL WWL Place Routed Route x1e6 x1e6 time WL x1e6 time Industrial UCLA Capo Capo-Fast Industrial UCLA Capo Capo-Fast Industrial UCLA Capo Capo-Fast Industrial UCLA Capo Capo-Fast Industrial UCLA Capo Capo-Fast Industrial UCLA Capo Capo-Fast Industrial UCLA Capo
579 3840 5382 6346 5558 3502 4196 7355 1120 1050 1055 624 615 701 What About MCNC Benchmarks? Too old for meaningful routability evaluation > 10 years old, no longer representative (Alpert 98) row-based layouts use variable-die Most published WLs are unreliable solutions not available different row configurations used
some placers place pads (on the boundary?) some assume given pad locations (which ones?) Capo runs on MCNC benchmarks (Bookshelf format) you can download Capo, run it and see solutions runtimes on a single Pentium III Xeon @550MHz avqlarge ( 25K cells, 33K nets) 4.5min golem3 (100K cells, 217K nets) 37 min What Did Not Work For Us Overlapping with bisections Fancy terminal propagation Explicit top-down look-ahead Improvements using analytical placement quadratic wirelength linear wirelength Using name-based hierarchies
improvement on one example out of many the circuit was unusually hard to partition possible interpretation: need to improve partitioner Placement Vcycling Conclusions Capo placer is scalable and competitive freely available for research and commercial use Better recursive bisection better routability improving RB still makes sense (e.g., as proposed) improving min-cut partitioning still makes sense Weighted wirelength is not a good objective better HPWL better routability - not clear! We draw conclusions only about min-cut
Folklore: analytical placements are hard to route Other WL minimization techniques may be better or worse Min-cut may be a better objective ! Open Questions Need transparent routability improvement not to affect wirelength of routable placements Is recursive bisection [done right] still the best method ? you can download Capo and compare http://vlsicad.cs.ucla.edu/GSRC/bookshelf/Slots/Pla cement
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