CECS470 - Rochester Institute of Technology

CECS470 - Rochester Institute of Technology

Memory Devices Read Only Memory (ROM) Structure of diode ROM Types of ROMs. ROM with 2-Dimensional Decoding. Using ROMs for Combinational Logic Read/Write Memory (Random Access Memory, RAM): Types of RAM: Static RAM (SRAM) Dynamic RAM (DRAM) SRAM Timing DRAM Timing EECC341 - Shaaban #1 Lec # 19 Winter 2001 2-14-2002 Read-Only Memory (ROM) A combinational circuit with n inputs and b outputs: Address n inputs A(n-1, ... , 0) 2n x b ROM b Data outputs

D(b-1, ... , 0) Programmable values determined by user Nonvolatile contents retained without power Uniform (Random) Access delay is uniform for all addresses EECC341 - Shaaban #2 Lec # 19 Winter 2001 2-14-2002 Read-Only Memory (ROM) Two views of ROM: ROM stores 2n words of b bits each, or ROM stores an n-input, b-output truth table Example: n=2 A1 A0 0 0 0 1 b=4 D3 D2 D1 D0 0 1 0 1 1 1 1 1 1 1 0 1

0 1 0 0 0 0 1 0 Stores 4 4-bit words, or stores 4 functions of 2 input variables EECC341 - Shaaban #3 Lec # 19 Winter 2001 2-14-2002 Internal Structure of 4 Diode ROM +5 V R3 A1 A0 2 to 4 Decoder R2 R1 R0 /w0 0101 /w1

1111 /w2 1 of n Word Lines 0001 /w3 1000 Bit Lines Diode 1 No Diode 0 D0 D1 D2 D3 EECC341 - Shaaban #4 Lec # 19 Winter 2001 2-14-2002 Mask ROM Types Of ROMs Connections made by the semiconductor vendor Expensive setup cost, Several weeks for delivery. High volume only Bipolar or MOS technology

PROM Programmable ROM Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses Bipolar technology One-time programmable EPROM Erasable Programmable ROM Charge trapped on extra floating gate of MOS transistors Exposure to UV light removes charge. Limited number of erasures (10-100) EEPROM (E2ROM) Electrically Erasable ROM Not RAM (relatively slow charge/discharge) limited number of charge/discharge cycles (10,000) Flash Memory Electronically erasable in blocks 100,000 erase cycles Simpler and denser than EEPROM EECC341 - Shaaban #5 Lec # 19 Winter 2001 2-14-2002

ROM Type Summary Type Technology Mask ROM NMOS,CMOS Read Cycle 20-200 ns Mask ROM Bipolar <100 ns PROM <100 ns Bipolar Write Cycle EPROM NMOS, CMOS 25-200 ns EEPROM NMOS 50-200 ns FLASH CMOS 25-200 ns

4 weeks 4 weeks 5 minutes 5 minutes 10 s/byte 10 s/block Comments Write once; low power Write once; high power; low density Write once; high power; no mask charge Reusable; low power; no mask charge 10,000 writes/location limit 100,000 erase cycles EECC341 - Shaaban #6 Lec # 19 Winter 2001 2-14-2002 Internal Structure of Transistor ROM Replace diodes with MOS transistors Change decoder to active-high outputs +5 V R3 R2 R1 R0 w3 Transistor 1 No transistor 0

1000 /D3 /D2 /D1 /D0 EECC341 - Shaaban #7 Lec # 19 Winter 2001 2-14-2002 EPROM and EEPROM Structure VDD Floating gate Active-high word lines Active-low bit lines EECC341 - Shaaban #8 Lec # 19 Winter 2001 2-14-2002 64 x 1 ROM with 2-Dimensional Decoding +5 V /w0 A5 A3 A2 A0

3 to 8 Decoder /w1 8x8 Diode Array /w7 0 7 8 to 1 mux D0 Almost square chip EECC341 - Shaaban #9 Lec # 19 Winter 2001 2-14-2002 A0 A1 Am-1 Row decode r Power on Am Am+1 Storage array Power

on Power on Column multiplexer An-1 /CS /OE Internal 2n x b ROM Structure Db-1 Db-2 D0 EECC341 - Shaaban #10 Lec # 19 Winter 2001 2-14-2002 Using ROMs for Combinational Logic Example A 3-input, 4-output combinational logic function: Inputs A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1

0 1 1 1 0 1 1 1 D3 1 1 1 0 0 0 0 1 Outputs D2 D1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 D0 0 1

1 1 1 0 0 0 8 ROM I0 I1 POL A0 A1 A2 D0 D1 D2 D3 Y0 Y1 Y2 Y3 Function: 2-to-4 Decoder with Polarity Control A2 = Polarity (0 = active Low, 1= active High) A1, A0 = I1, I0 (2-bit input ) D3...D0 = Y3...Y0 (4-bit decoded output) EECC341 - Shaaban #11 Lec # 19 Winter 2001 2-14-2002 Read/Write Memory (RWM / RAM)

RWM = RAM (Random Access Memory) Highly structured like ROMs Can store and retrieve data at (relatively) the same speed Static RAM (SRAM) retains data in latches (while powered) Dynamic RAM (DRAM) stores data as capacitor charge; all capacitors must be recharged periodically (refresh). Volatile Memory: Both Static and Dynamic RAM Nonvolatile Memory: Data retained when power lost = ROMs, NVRAM (w/battery), Flash Memory EECC341 - Shaaban #12 Lec # 19 Winter 2001 2-14-2002 Basic Structure of SRAM 2n x b RAM A0 A1 An-1 DIN0 DIN1 DOUT0 DOUT1 DINb-1 DOUTb-1 CS OE WE

Address/Control/Data Out lines like a ROM (Reading) + Write Enable (WE) and Data In (DIN) (Writing) EECC341 - Shaaban #13 Lec # 19 Winter 2001 2-14-2002 One Bit of SRAM D /SEL /WR C IN Q OUT IN OUT SEL WR SEL and WR asserted IN data stored in D-latch (Write) SEL only asserted D-latch output enabled (Read) SEL not asserted No operation EECC341 - Shaaban #14 Lec # 19 Winter 2001 2-14-2002

DIN3 DIN2 DIN1 DIN0 0 IN 1 8x4 SRAM 3-to-8 Decoder A2 A1 A0 2 1 0 4 IN WR WR WR OUT IN OUT

IN OUT IN SEL SEL SEL SEL WR WR WR WR OUT IN OUT IN OUT IN SEL SEL SEL

SEL WR WR WR WR IN OUT IN OUT IN OUT IN SEL SEL SEL SEL WR WR WR WR OUT

IN OUT IN OUT IN SEL SEL SEL SEL WR WR WR WR OUT IN OUT IN OUT IN SEL

SEL SEL SEL WR WR WR WR IN 7 OUT WR IN 6 IN SEL IN 5 OUT SEL IN 3

IN SEL IN 2 OUT SEL OUT IN OUT IN OUT IN SEL SEL SEL SEL WR WR WR WR IN

OUT IN OUT IN OUT IN SEL SEL SEL SEL WR WR WR WR OUT OUT OUT OUT OUT OUT

OUT OUT /WE /CS /OE DOUT3 DOUT2 EECC341 DOUT1 - Shaaban DOUT1 #15 Lec # 19 Winter 2001 2-14-2002 SRAM Timing During READ, outputs are combinational functions of ADDR, CS, OE (like ROM) Inputs can freely change without problems (except for propagation delay from last input change to output) During WRITE, data stored in latches, NOT FFs. Thus, Setup & Hold on Data IN relative to trailing edge of /WR Address must be stable for setup time before /WR asserted, and for hold time after /WR deasserted to prevent spraying data to multiple rows /WR asserted when BOTH /CS and /WE asserted /WR deasserted when EITHER /CS or /WE deasserted EECC341 - Shaaban #16 Lec # 19 Winter 2001 2-14-2002 READ Timing (SRAM) max(tAA, tACS) ADDR stable

stable stable tAA /CS t OH tACS /OE tAA DOUT t OZ valid Primary Spec for SRAMs t OE tOZ valid tOE valid EECC341 - Shaaban #17 Lec # 19 Winter 2001 2-14-2002 WRITE Timing (SRAM) (WE-controlled write) ADDR (CS-controlled write) stable stable

tCSW tAS tCSW /CS tAS tWP tAH tWP tAH /WE tDS DIN tDH valid tDS tDH valid EECC341 - Shaaban #18 Lec # 19 Winter 2001 2-14-2002 Example: 16 x 1 SRAM 4 x 4 Array D1 0 2-to-4 Decoder 1

A1 A0 1 0 2 3 A3-A2 /WE /CS /OE IN OUT SEL IN OUT SEL IN OUT SEL IN OUT SEL WR WR WR WR IN OUT SEL IN OUT SEL IN OUT

SEL IN OUT SEL WR WR WR WR IN OUT SEL IN OUT SEL IN OUT SEL IN OUT SEL WR WR WR WR IN OUT SEL IN OUT SEL IN OUT SEL

IN OUT SEL WR WR WR WR 2-to-4 Decoder S E 4-to-1 Mux DO EECC341 - Shaaban #19 Lec # 19 Winter 2001 2-14-2002 64K x 8 RAM with 2-D Decoding A 9 to 512 Decoder 512 512 128 128

A 512 128 128 512 128 512 1024 Array 128 128 to 1 Mux 128 to 1 Mux D0 D1

128 to 1 Mux D7 EECC341 - Shaaban #20 Lec # 19 Winter 2001 2-14-2002 Classic DRAM Organization EECC341 - Shaaban #21 Lec # 19 Winter 2001 2-14-2002 Logical Diagram of A Typical DRAM EECC341 - Shaaban #22 Lec # 19 Winter 2001 2-14-2002 64K x 1 DRAM bit line word line 256 x 256 array Row decode r 1-bit DRAM cell Row ADDR 8 ADDR /RAS /CAS /WE

/ Control Col ADDR Control Row register, Data mux/demux 64K x 1 DRAM 8 / ADDR Din RAS CAS WE Dout EECC341 - Shaaban #23 Lec # 19 Winter 2001 2-14-2002 Standard Asynchronous DRAM Read Timing Valid Data tRAC: Minimum time from RAS (Row Access Strobe) line falling to the valid data output. Usually quoted as the nominal speed of a DRAM chip. For a typical 4Mb DRAM tRAC = 60 ns tRC: Minimum time from the start of one row access to the start of the next. tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns EECC341 - Shaaban #24 Lec # 19 Winter 2001 2-14-2002 Four Key DRAM Timing Parameters tRAC: Minimum time from RAS (Row Access Strobe) line

falling to the valid data output. Usually quoted as the nominal speed of a DRAM chip For a typical 4Mb DRAM tRAC = 60 ns tRC: Minimum time from the start of one row access to the start of the next. tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns tCAC: minimum time from CAS (Column Access Strobe) line falling to valid data output. 15 ns for a 4Mbit DRAM with a tRAC of 60 ns tPC: minimum time from the start of one column access to the start of the next. About 35 ns for a 4Mbit DRAM with a tRAC of 60 ns EECC341 - Shaaban #25 Lec # 19 Winter 2001 2-14-2002 Simplified Asynchronous DRAM Read Timing Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html EECC341 - Shaaban #26 Lec # 19 Winter 2001 2-14-2002 Modern DRAM Timing Fast-Page Mode, FPM DRAM (One RAS, multiple CAS) Multiple bits of a row can be written before rewrite Complex control, but much faster Extended Data Out, EDO DRAM (One RAS, multiple CAS) Latches the column address so that the next address can be prepared while the output is read Saves ~10ns/read, and increase of 10-15% Even more complex control. SDRAM - Synchronous DRAM Unlike normal DRAM, SDRAM is clocked. Multiple signals and banks (row-address registers) allow pipelined operation

EECC341 - Shaaban #27 Lec # 19 Winter 2001 2-14-2002 Page Mode DRAM: Motivation EECC341 - Shaaban #28 Lec # 19 Winter 2001 2-14-2002 Fast Page Mode DRAM: Operation EECC341 - Shaaban #29 Lec # 19 Winter 2001 2-14-2002 Simplified Asynchronous Fast Page Mode (FPM) DRAM Read Timing FPM DRAM speed rated using tRAC ~ 50-70ns Typical timing at 66 MHZ : 5-3-3-3 For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 3 = 176 Mbytes/sec Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html EECC341 - Shaaban #30 Lec # 19 Winter 2001 2-14-2002 Simplified Asynchronous Extended Data Out (EDO) DRAM Read Timing Extended Data Out DRAM operates in a similar fashion to Fast Page Mode DRAM except the data from one read is on the output pins at the same time the column address for the next read is being latched in. EDO DRAM speed rated using tRAC ~ 40-60ns Typical timing at 66 MHZ : 5-2-2-2 For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 2 = 264 Mbytes/sec EECC341 - Shaaban

Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html #31 Lec # 19 Winter 2001 2-14-2002 Synchronous Dynamic RAM (SDRAM) Organization SDRAM speed is rated at max. clock speed supported: 66MHZ = PC66 100MHZ = PC100 133MHZ = PC133 150MHZ = PC150 EECC341 - Shaaban #32 Lec # 19 Winter 2001 2-14-2002 Simplified SDRAM Read Timing Typical timing at 133 MHZ (PC133 SDRAM) : 4-1-1-1 For bus width = 64 bits = 8 bytes Max. Bandwidth = 133 x 8 = 1064 Mbytes/sec EECC341 - Shaaban Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-6.html #33 Lec # 19 Winter 2001 2-14-2002 RAM Summary SRAM: Fast Simple Interface Moderate bit density (4 gates 4 to 6 transistors) Moderate cost/bit DRAM (Dynamic RAM): moderate speed complex interface High bit density (1 transistor cell)

Low cost/bit Small systems or very fast applications (cache memory) Large Memories: PCs Mainframes EECC341 - Shaaban #34 Lec # 19 Winter 2001 2-14-2002

Recently Viewed Presentations

  • B L Lifesciences BL Lifesciences Medical Device Manufacturing

    B L Lifesciences BL Lifesciences Medical Device Manufacturing

    State of Art Building designed in Compliance to all Statutory / Regulatory requirements , our product requirements & future growth in mind Total built up area : 68,000 sq. ft. Ware House : 25,000 sq. ft. Manufacturing facility Current Staff...
  • Burns and Skin Pathology - Hanover Community School ...

    Burns and Skin Pathology - Hanover Community School ...

    Burns and Skin Pathology ... of tissue Genetic Mutations that diminish skin function and structure Infectious disease Microorganisms damage tissues and organs Basal Cell Carcinoma Uncontrolled growths or lesions that arise in the skin's basal cells Often look like open...
  • Présentation PowerPoint

    Présentation PowerPoint

    * * * * * * * * * * * * * Heureusement les solidarités aussi se mondialisent! La Marche mondiale des femmes (MMF) est un mouvement mondial rassemblant des groupes et organisations de femmes de terrain œuvrant pour...
  • privecsg-14-0014-00-0000 IEEE 802 Privacy Threat Model Date: [2014-10-22]

    privecsg-14-0014-00-0000 IEEE 802 Privacy Threat Model Date: [2014-10-22]

    Misattribution. Misattribution occurs when data or communications related to one individual are attributed to another. Misattribution in the protocol context comes as a result of using inadequate or insecure forms of identity or authentication, and is sometimes related to spoofing
  • Friedrich Nietzsche 1844 - 1900 By: Amy Ahonen,

    Friedrich Nietzsche 1844 - 1900 By: Amy Ahonen,

    1864- Started at the University of Bonn gave up theology and went on to study classical languages on a deeper level and get a career in Physiology. 1865- Started at the University of leipzig and devoted himself to studying. 1868-...
  • Fish Consumption & Water Quality Don A. Essig,

    Fish Consumption & Water Quality Don A. Essig,

    Fish consumption data for Idaho consists of EPA's 2002 national survey, and CRITFIC's 1994 survey of four tribes, one of which was the Nezperce in Idaho. When we looked at fish consumption data n 2005 it was the same story...
  • Surviving Sexual Abuse: Counseling Adults Abused as Children

    Surviving Sexual Abuse: Counseling Adults Abused as Children

    Restoring the Shattered Self: Complex Traumatic Stress Disorder (CTSD) and Missionaries Mental Health and Missions, 2013 Heather Davediuk Gingrich, Ph.D.
  • Do-Now: &quot;The Ideal person is expected to take as much trouble ...

    Do-Now: "The Ideal person is expected to take as much trouble ...

    Do-Now:"The Ideal person is expected to take as much trouble to discover what is rights as lesser men take to discover what will pay.". Would Confucian ideas such as the one expressed in this quote influence the Zhou dynasty? Why...