Experimental Results of CC2 Charge Sensitive Preamplifier
Meeting on GERDA Phase II Front-End Electronics R&D Status on the Fully Integration of the Front-End Electronics Milano Bicocca - 16/4/2010 ASIC designed for the Gerda Experiment - Multi Ch. Fully Integrated CMOS ASIC CSA (Heidelberg, 2007) http://cdsweb.cern.ch/record/1034317/files/p515.pdf - Single Ch. Fully Integrated CMOS ASIC CSA (Milano, 2007) http://www.mpi-hd.mpg.de/gerda/public/2008/c08_IEEE_dresden_cmos_sr.pdf - Single Ch. JFET-CMOS ASIC CSA (Milano, 2007) http://www.mpi-hd.mpg.de/gerda/public/2008/c08_IEEE_dresden_preamp_fc.pdf - Multi Ch. JFET-CMOS ASIC CSA (Milano, 2008) http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5401678&queryText %3Dpullia+zocca%26openedRefinements%3D*%26searchField%3DSearch+All - Multi Ch. JFET-CMOS ASIC CSA (Milano, 2009) ASIC Development in Heidelberg
Design Features: - 4 channels - differential voltage output - gain 5.8 mV/fC = 310 mV/MeV (Ge) - dynamic range = 11 MeV (Ge) - integrate feedback C and R - programmable R up to 2 G @LNTLNT - I2C interface for programming - noise (Tsh= 10 s, Cdet= 30 pF) @LNTRT: ENC ~ 220 e 1.5 keV (Ge) @LNTLNT: ENC ~ 110 e (expected) Results: - ASIC works @LNTLNT (77 K) - gain 15% lower, perfect linearity - programmable R worked ! - large noise (Tsh= 10 s, Cdet= 30 pF) @LNTLNT: ENC ~ 500 e - evidence of noise correlation between channels - noise (Tsh= 10 s, Cdet= 30 pF) calculated as (Out1 Out2) / 2 @LNTLNT: ENC ~ 240 e Testboard Kapton with ASIC
Conclusion: - large common mode noise - despite some effort: reason unclear not usable as it is - designer left collaboration stopped ASIC development ASIC Development in Milano Design Features: - 1 channel - fully differential ASIC design - CSA + Fully Differential Amplifier - FDA with differential output (50 ) - power supplies = 2.5 V - power consumption < 50 mW - gain 1 mV/fC = 54 mV/MeV (Ge) - discrete C (for testing) and R - pulsed-reset operation mode (no R) - noise (Tsh = 50 s, Cdet = 33 pF) @LNTRT: ENC ~ 200 e 1.4 keV (Ge) @LNTLNT: ENC ~ 100 e (expected) Results: - ASIC works both at RT and LNT - tested with C = 1 pF and R = 300 M - dynamic range > 20 MeV (Ge)
- shaping time of 50 s is unrealistic - large noise (Tsh = 12 s, Cdet = 33 pF) @LNTLNT: ENC ~ 250 e - energy resolution with SUB det. (Milano 2008, Tsh = 8 s) @LNTLNT: 3 kev @LNT1.33 Mev ( Co) 60 PCB with ASIC Conclusion: - evidence of fundamental noise only - bad design choice of long shaping time determined too a low input p-mos transconductance of 2 mS (vs better then 10 mS of BF862) not usable as it is - in order to concentrate on better CSA stopped development Set-up of the Gerda Experiment L 10 m Electronics
CSA (Flash ADC, ) L 10 m Room Temperature Radioactivity issue: Ge det. (Material Activity * Volume) r2 CSA requirements: Liquid Argon Cryogenic Temperature Bandwidth ( > 10 MHz, 30 ns rise time) Noise (ENC < 150 e @LNTLNT, Tsh =10 s) Power consumption < 50 mW/channel Cross-talk between channels < 1%
Set-up of the Gerda Experiment L 10 m Electronics ??? (Flash ADC, ) L 10 m Room Temperature CSA Radioactivity issue: (Material Activity * Volume) Ge det. r2 CSA requirements:
Liquid Argon Cryogenic Temperature Bandwidth ( > 10 MHz, 30 ns rise time) Noise (ENC < 150 e @LNTLNT, Tsh =10 s) Power consumption < 50 mW/channel Cross-talk between channels < 1% Cryogenic operation Radioactivity issue: (material, distance, volume) Integration = Miniaturization CSA far from detector means: increased noise reduced bandwidth From the viewpoint of the CSA design alone: closer is better increased cross-talk? 100 mm
2 mm Volume reduction 10000 Critical distance reduced by a factor of 100 Silicon Integration easy for: difficult for: (Active Devices) CMOS JFET (available technology?) BJT (not suitable for LNT) (Passive Devices) Resistors (up to a few MOhm) Capacitors (up to a few pF) (Active Devices) Low Noise MOS (P Type) (< 1 nV/Hz eq. voltage noise) (Passive Devices) Resistors (above 100 MOhm) (large area or distortion with CMOS) Capacitors (above 100 pF)
Inductors also to be considered: Interface between ASIC and outside world (bonding wires, glue, PCB, copper shield, connectors, pins, cables, ecc.) Components of a CSA (on paper) not easy to integrate Input Output Complete integration of a CSA with reasonable performances in terms of bandwidth, noise, power consumption, etc. is a difficult task but still possible Components of a CSA (real world) bonding wires connector pins PCB (teflon + copper + gold) cables (teflon + copper)
cables (teflon + copper) Because cables have to be thin, they are far from ideal: High resistivity of central wire ( 1 /m) and shield ( 0.2 /m) High attenuation (10% for 10 m long cables, 50 terminated) Electro-magnetic shielding not so effective (e.g. FM radio in Milano) Low voltage levels on board not perfectly the same as on the outside power supply Components of a CSA (real world) decoupling capacitors Most promising capacitors seems to be tantalum based Number of strictly required decoupling capacitors may change across different CSAs Reasonable values are n = 4 to 10; C = 10 F; (VDC = 6 v) Insufficient LVPS decoupling may generate: noise/instability in single channel CSA noise/instability + cross-talk in multi channels CSA Complex Optimization Problem (example) integrate CSA (less volume) radioactivity thinner cables
(less volume) 3 Ch. CSA (less volume) cross-talk disturbances noise signal integrity LVPS in parallel 50 term. receiver more decoupling capacitors radioactivity Basic scenario to start with L1
CSA bandwidth, noise 5/6 + 1 wires driver not very critical not very critical with receiver is 50 terminated Among open issues are: Single or multi channels (n) CSA Discrete or integrated electronics design For every reasonable configuration, determine radioactivity issue ( L ) Easy to deal with mechanical design Robustness, time, cost receiver
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