From Data to Circuits

The CS 5 Times Professor Loses Drinking Contest in Local Bar Pomona (Penguin Press): A little-known professor from a local college was found under the table here Penguin celebrates win after coming in second in a game that required himover professor. to consume twice as many mugs of liquid as his opponent. His mistake was to agree to compete on the basis of mug count, explained the winner. He left the choice of mugs up to me. In other news, a second professors dog was found soaking wet and yelping in a neighbors back yard. The odor was overpowering, said the neighbor. We had to hose the animal down before we could approach it. Police are investigating a rumor that the canine had been attacked by a More on Circuits! Last time 1. String representation 2. From Boolean functions to digital circuits Today 1. A circuit for adding 2. A circuit simulator 3. How logic gates really work 4. Universality of logic gates 5. Memory A Circuit for Adding! Base 2 Addition 0 + 1 1 0 0 0

1 1 0 carry out FA sum A Circuit for Adding! Base 2 Addition 0 + 1 1 0 0 0 1 1 0 FA FA FA FA Cool, but how do we build a FA? A Circuit for Adding! Base 2 Addition 0 + 1 1 0 0 0

x y carryin sum carryout 1 1 0 0 0 FA FA FA FA x y carryin FA carryout sum 0 0 0 0 0 1 0 1 Logisim: A Digital Logic Simulator Implementing Gates with Relays NOT Gate A Figures courtesy of HowStuffWorks.com Q=A 6v power And AND A

AB B 6v power Figure courtesy of HowStuffWorks.com Integrated Circuits 3mm http://personalpages.manchester.ac.uk/staff/p.dudek/projects/scamp http://www.helicon.co.uk AND, OR, NOT Is a Universal Set De Morgans Laws: xy=x+y x+y = x y Are there other universal sets of gates? Augustus De Morgan 1806-1871 By Sophia Elizabeth De Morgan - Memoir of Augustus De Morgan, Public Domain https://commons.wikimedia.org/w/index.php?curid=4722207 The Aliens Life Advice Get your eyes off the ground! Your poor sore nose will appreciate it...and so will the people you look at. Sending a Message to Prof. Ben Worksheet! A 1-Bit Memory

This stuff is truly unforgettable! OR + NOT = NOR A 1-Bit Memory Setting a 1-Bit Memory Initializing a 1-Bit Memory From S-R Latches to D-Latches > A Random-Access Memory (RAM) A 512K x 8 RAM (About 4.2 million bits) small! A Random-Access Memory (RAM) 2 address bits 3 data bits (in) 0 1 0 1 1 1 0 0 0 Read Write 0 0 1

3 data bits (out) A Random-Access Memory (RAM) 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch D Q D Latch Q D

Q D Latch Strobe D D Latch Q D Q D Latch Strobe D Strobe Q Strobe Strobe D Strobe D Latch Strobe D

Read Write D Strobe D 3 data bits (in) Q D Latch Q D Strobe Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe

D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch D Q D Latch Q D Q D Latch Strobe D D Latch Q

D Q D Latch Strobe D Strobe Q Strobe Strobe D Strobe D Latch Strobe D Read Write D Strobe D 3 data bits (in)

Q D Latch Q D Strobe Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D

Latch Q D D Latch D Q D Latch Q D Q D Latch Strobe D D Latch Q D Q D Latch Strobe D Strobe

Q Strobe Strobe D Strobe D Latch Strobe D Read Write D Strobe D 3 data bits (in) Q D Latch Q D Strobe

Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch D Q D

Latch Q D Q D Latch Strobe D D Latch Q D Q D Latch Strobe D Strobe Q Strobe Strobe D Strobe D

Latch Strobe D Read Write D Strobe D 3 data bits (in) Q D Latch Q D Strobe Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits

D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch D Q D Latch Q D Q D Latch Strobe

D D Latch Q D Q D Latch Strobe D Strobe Q Strobe Strobe D Strobe D Latch Strobe D Read Write D Strobe

D 3 data bits (in) Q D Latch Q D Strobe Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe

Q Q D Latch Q D D Latch D Q D Latch Q D Q D Latch Strobe D D Latch Q D Q D Latch

Strobe D Strobe Q Strobe Strobe D Strobe D Latch Strobe D Read Write D Strobe D 3 data bits (in) Q D Latch Q

D Strobe Q D Latch 3 data bits (out) A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch

D Q D Latch Q D Q D Latch Strobe D D Latch Q D Q D Latch Strobe D Strobe Q Strobe Strobe

D Strobe D Latch Strobe D Read Write D Strobe D 3 data bits (in) Q D Latch Q D Strobe Q D Latch 3 data bits (out)

A Random-Access Memory (RAM) Decoder 2 address bits D D Latch Strobe D Latch Strobe D Latch Strobe Q Q D Latch Q D D Latch D Q D Latch Q D Q

D Latch Strobe D D Latch Q D Q D Latch Strobe D Strobe Q Strobe Strobe D Strobe D Latch Strobe D Read

Write D Strobe D 3 data bits (in) Q D Latch Q D Strobe Q D Latch 3 data bits (out)

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