JTAG Technologies Overview - CAS

JTAG Technologies Overview - CAS

UNLOCKING THE POWER OF BOUNDARYSCAN JTAG Overview Presentation 1 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. World Wide Users 3Com ABB August Systems AGFEO Alcatel AscomTelecom. Atlas Copco Barco Graphics Blaupunkt Bofors Celestica Compaq Datex ECI EKB JTAG Overview Presentation Ericsson Matra Philips Ericsson Intracom Matra Communications

MedicalSystems Force Computer Matra-Ericsson T. Pioneer Fujitsu Microelectronics Matsushita Polytechnico di T. Fujitsu Telecom MET Rolls Royce GEC Alsthom Mitsubishi Electric Siemens Medical Harris Motorola Siemens Nixdorf Hewlett-Packard NEC Technologies Sogitec Hirschmann Nokia Mobile Comm. Solectron Hitachi Consumer NORTEL

Sony Hitachi Microsystems NTT Sun Microsystems Honeywell Regels. Parsytec Telefunken Italtel Research Centre Philips BCS Thomson Japanese Radio Corp. Philips CE Tokyo MITC Kontron Philips CFT Toshiba MarPoss 2 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. Value

Uniform tools across multiple departments Rapid development cycles, shorter time-to-market High-speed production rates Low initial investment and low cost of ownership Comprehensive supporting services JTAG Overview Presentation 3 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. IEEE 1149.1 Boundary-Scan Standard Adopted in 1990 by the IEEE as Standard 1149.1 Prepared by the Joint Test Action Group (JTAG) Originally for testing boards and devices Provides a serial 4-wire (5th is optional) interface, regardless of device complexity Semi-conductor manufacturer responsible for: Designing device for compatibility Providing BSDL file Many of todays key components contain Boundary-Scan Microprocessors, CPLDs, ASICs, FPGAs, DSPs, etc. Flash isnt directly compatible, but programmable JTAG Overview Presentation 4 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc..

Boundary-Scan Market Drivers Drivers Lack of access for testing via conventional methods Desire to program devices after board assembly Need for commonality of platforms Pin count 2000s uBGA 1980s 1970s Requirement for system-level testing PLCC DIP Complexity JTAG Overview Presentation 5 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. BR BR BR BR BR BR BR

BR BoundaryScan at the Chip Level Internal Core Logic BR BR BR TDI TDO Bypass Instruction Reg. ID Register TMS TAP controller TCK JTAG Overview Presentation 6 October 2001 Implemented in the ICs Adds logic to the chips, allowing data from an external source to be loaded into ... and read from the device pins Accesses a large number of previously unavailable test points Many of ICs today contain boundary-scan Copyright 2001 JTAG Technologies

JTAG T e c h n o l o g i e s Inc.. Applied to the PCB Board Testing Scan Infrastructure--verifies the Interconnection -- paths between scan devices Clusters -- non-scan portions of the board such as edge connectors and other logic Memory -- address, data, and control lines to memory arrays Test Access Port test system and the scan chain CPLD Flash In-System Programming CPLDs--all of the major brands Flash--all types, at high speed JTAG Overview Presentation 7 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. FAST Flash Programming Programming Time (seconds)

140.0 Programming times of Intel 28F016 16 Mb Flash memory via scan chains at various TM shift frequencies using AutoWrite 130.0 120.0 110.0 Scan chain consisting of 165 boundary-scan cells @ 12 Volt Vpp 100.0 Scan chain consisting of 165 boundary-scan cells @ 5 Volt Vpp 90.0 Scan chain consisting of 251 boundary-scan cells 80.0 Intrinsic programming time @ Vpp=12 Volt 70.0 Intrinsic programming time @ Vpp=5 Volt 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.0 2.5 5.0 7.5 10.0

12.5 15.0 17.5 20.0 22.5 25.0 TCK Frequency (MHz) (Close to theoretical speeds, 1-3 seconds per megabit, depending on board design) JTAG Overview Presentation 8 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. Product Lineup Test: Netlist BSDLs Cluster Descriptions Basic Standard Full Professional Flash Programming: Standard Professional PLD Programming: Standard Full

Application Development Packages Application Files UUT Production Packages Stand-Alone Server Integration Packages JTAG Overview Presentation 9 October 2001 BoundaryScan Controller Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. BOUNDARY-SCAN TEST CHARACTERISTICS Achievable Fault-coverage - Infrastructure Test: 100% Opens - Interconnect Test: 100% Shorts - Memory Interconnection Test: 100% Stuck 0/1 - Clusters: a) Use PCB SIM (TSSI) w/Active Test b) Use Active Test w/ golden PCB

Wrong/Missing Diagnostics Automatic To the Pin on the Part at fault! Components Test Preparation Time: Much Faster Pin-Level (5-7 days for most complex designs) Shorted Nets Size of Capital Investments, < ICT Components JTAG Overview Presentation 10 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. The Power of Boundary-Scan Testing Overcomes the Access Problem Simple TAP interface vs. parallel test points Detects Structural PCB Defects Shorts, Opens, Missing Components, Stuck 0/1 Connector, cluster, memory interconnection testing possible Automated Test Pattern Generation and Diagnostics Coverage Can be High, Depending on Scannable Parts

JTAG Overview Presentation 11 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc.. Summary of Benefits Can provide significant savings Allows test access to complex SMT boards Integrates development, manufacturing, test, and programming Simplifies inventory management, reduces device handling Optimizes use of expensive ATE equipment Less complex ATE and/or test fixtures Rapid test and programming development JTAG Overview Presentation 12 October 2001 Copyright 2001 JTAG Technologies JTAG T e c h n o l o g i e s Inc..

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