MC542 Organização de Computadores Teoria e Prática

MC542 Organização de Computadores Teoria e Prática

MC542 Organizao de Computadores Teoria e Prtica 2007 Prof. Paulo Cesar Centoducatte [email protected] www.ic.unicamp.br/~ducatte MC542 A-1.1 MC542 Arquitetura de Computadores Introduo; Conjunto de Instrues DDCA - (Captulo 6) COD - (Captulo ) MC542 A-1.2 Arquitetura de Computadores Sumrio Introduo O que arquitetura de computadores Tendncias

Lei de Moore Capacidade Microprocessadores Desempenho dos processadores Capacidade e Velocidade das Memrias Conjuntos de Instrues Introduo MC542 A-1.3 O que Arquitetura de Computadores? 1950s a 1960s: Cursos de AC Aritmtica Computacional 1970s a meados dos anos 1980s: Cursos de AC Projeto do Conjunto de Instrues (ISA), especialmente voltado para compiladores 1990s a 2000s: Cursos de AC Projeto de CPU, Sistemas de Memrias, Sistemas de I/O, Multiprocessadores. MC542 A-1.4 Tendncias Gordon Moore (fundador da Intel), em 1965 observou que o nmero de transistores em um chip dobrava a cada ano (Lei de Moore) Continua valida at os dias de hoje (porm est encontrando a barreira trmica) O desempenho dos processadores, medidos por diversos benchmarks, tambm tem crescido de forma acelerada. A capacidade das memrias tem aumentado

significativamente nos ltimos 20 anos (E o custo reduzido) MC542 A-1.5 Qual a Razo Desta Evoluo nos ltimos Anos? Desempenho Avanos tecnolgicos Domnio de CMOS sobre as tecnologias mais antigas (TTL, ECL) em custo e desempenho Avanos nas arquiteturas RISC, superscalar, VLIW, RAID, Preo: Baixo custo devido Desenvolvimento mais simples CMOS VLSI: sistemas menores, menos componentes Alto volume (escala) ..... MC542 A-1.6 Tendncias: Lei de Moore Transistors Per Chip 1.E+08 Pentium 3 Pentium Pro 1.E+07

Pentium II Power PC G3 Pentium 486 1.E+06 Power PC 601 386 80286 1.E+05 8086 1.E+04 4004 1.E+03 1970 1975 1980 1985 1990 1995 2000

2005 MC542 A-1.7 Tendncia Tecnolgica: Capacidade Microprocessadores 100000000 Alpha 21264: 15 million Pentium Pro: 5.5 million PowerPC 620: 6.9 million Alpha 21164: 9.3 million Sparc Ultra: 5.2 million 10000000 Transistors Moores Law Pentium i80486 1000000 i80386 i80286 100000 CMOS: Die size: 2X a cada 3 anos i8086

10000 i8080 i4004 1000 1970 1975 1980 1985 1990 1995 2000 Year MC542 A-1.8 Tendncias Desempenho dos processadores 5000 Alpha 6/833 4000 3000 2000 2000

99 98 97 96 95 94 93 92 91 IBM RS/ 6000 90 89 88 0 Sun MIPS -4/ M

260 2000 87 1000 DEC Alpha 5/500 DEC AXP/ DEC Alpha 21264/600 500 DEC Alpha 4/266 MC542 A-1.9 Tendncias Capacidade das Memrias size 1000000000 100000000 ano 1980 1983 1986 1989 1992 1996 2000 Bits

10000000 1000000 100000 10000 Mbyte cycle time 0.0625 250 ns 0.25 220 ns 1 190 ns 4 165 ns 16 145 ns 64 120 ns 256 100 ns 1000 1970 1975 1980 1985 1990

1995 2000 Year MC542 A-1.10 Tendncias Velocidade Para a CPU o crescimento da velocidade tem sido muito acelerado Para Memria e disco o crescimento da velocidade tem sido modesto Isto tem levado a mudanas significativas nas arquiteturas, SO e mesmo nas prticas de programao. Capacidade Speed (latency) Lgica 2x em 3 anos 2x em 3 anos DRAM 4x em 3 anos

2x em 10 anos Disco 4x em 3 anos 2x em 10 anos MC542 A-1.11 Conjunto de Instrues O ISA a poro da mquina visvel ao programador (nvel de montagem) ou aos projetistas de compiladores software instruction set hardware 1. Quais as vantagens e desvantagens das diversas alternativas de ISA. 2. Como as linguagens e compiladores afetam (ou so afetados) o ISA. 3. Arquitetura MIPS como exemplo de arquitetura RISC. MC542 A-1.12 Introduo - ISA

software instruction set Interface entre o Hardware e o Usurio hardware MC542 A-1.13 Evoluo dos ISAs As maiores vantagens em uma arquitetura, em geral, so associadas com as mudanas do ISA Ex: Stack vs General Purpose Registers (GPR) Decises de projeto que devem ser levadas em considerao: tecnologia organizao linguagens de programao tecnologia em compiladores sistemas operacionais MC542 A-1.14 Projeto de um ISA 5 aspectos principais

Nmero de operandos (explcitos) (0,1,2,3) Armazenamento do Operando. Aonde ele est? Endereo Efetivo. Como especificado? Tipo & Tamanho dos operandos. byte, int, float, como eles so especificados? Operaes add, sub, mul, como so especificadas? MC542 A-1.15 Projeto de um ISA Outros aspectos Sucessor Como especificado? Condies Como so determinadas? Codificao Fixa ou Vriavel? Tamanho? Paralelismo MC542 A-1.16 Classes bsicas de ISA Accumulator: 1 address

1+x address x] Stack: 0 address add A acc acc + mem[A] acc acc + mem[A + tos tos + next addx A add General Purpose Register: 2 address add A B 3 address add A B C EA(A) EA(A) EA(A) + EA(B) EA(B) + EA(C) Instrues da ALU podem ter dois ou trs operandos.

Load/Store: 0 Memory load R1, Mem1 load R2, Mem2 add R1, R2 1 Memory add R1, Mem2 Instrues da ALU podem ter 0, 1, 2, 3 operandos. MC542 A-1.17 Classes bsicas de ISA Cdigo nas diferentes classes de endereamento para: C = A + B. Stack Accumulato r Register (Register-memory) Push A

Load A Load R1, A Load R1, A Push B Add B Add R1, B Load R2, B Add Store C Store Add R3, R1, R2 Pop C

C, R1 Register (load-store) Store C, R3 MC542 A-1.18 Tipos de Mquinas MC542 A-1.19 Exemplos de ISAs Machine EDSAC Number of general-purpose registers 1 Architectural style Year Accumulator 1949 IBM 701

1 Accumulator 1953 CDC 6600 IBM 360 8 16 Load-store Register- memory 1963 1964 DEC PDP-8 1 Accumulator 1965 DEC PDP-11 Intel 8008 Motorola 6800 8 1 2

Register- memory Accumulator Accumulator 1970 1972 1974 DEC VAX 16 Register- memory, memory-memory 1977 Intel 8086 Motorola 68000 1 16 Extended accumulator Register- memory 1978 1980 Intel 80386 8 Register- memory

1985 MIPS HP PA-RISC SPARC PowerPC DEC Alpha 32 32 32 32 32 Load-store Load-store Load-store Load-store Load-store 1985 1986 1987 1992 1992 MC542 A-1.20 Modos de Endereamento Interpretando endereos de memria Qual objeto acessado em funo do endereo e

qual o seu tamanho? Objetos endereados a byte um endereo referese ao nmero de bytes contados do incio da memria. Little Endian o byte cujo endereo xx00 o byte menos significativo da palavra. Big Endian o byte cujo endereo xx00 o mais significativo da palavra. Alinhamento o dado deve ser alinhado em fronteiras iguais a seu tamanho. address / sizeof (datatype) == 0 bytes pode ser alinhado em qualquer endereo inteiros de 4 bytes so alinhados em endereos mltiplos de 4 MC542 A-1.21 Modos de Endereamento Register direct Ri Immediate (literal) v Direct (absolute) M[v] Register indirect

M[Ri] Base+Displacement M[Ri +v] Base+Index M[Ri + Rj] Scaled Index M[Ri + Rj*d +v] Autoincrement M[Ri++] reg. file Autodecrement M[Ri--] Memory indirect M[ M[Ri] ] memria MC542 A-1.22 Modos de Endereamento MC542 A-1.23 Operaes em um ISA Tipo Exemplo Arithmetic and logical and, add Data transfer move, load Control branch, jump, call System system call, traps

Floating point add, mul, div, sqrt Decimal add, convert String move, compare Multimedia - 2D, 3D? e.g., Intel MMX and Sun VIS MC542 A-1.24 Uso de Operaes em um ISA Integer average (% total executed) Rank 80x86 instruction 1 load 22% 2 3 4 5 6 7 8

9 10 conditional branch compare store add and sub move register-register call return 20% 16% 12% 8% 6% 5% 4% 1% 1% 96% Total FIGURE 2.11 The top 10 instructions for the 80x86. MC542 A-1.25 Instrues de Controle (20% das instrues so desvios condicionais)

Control Instructions: tomar ou no aonde o alvo link return address salvar ou restaurar Instrues que alteram o PC: (condicional) branches, (incondicional) jumps chamadas de funes, retorno de funes system calls, system returns MC542 A-1.26 Instrues de Desvio MC542 A-1.27 Tipos e Tamanhos dos Operandos O tipo do operando, em geral, codificado no opcode LDW significa loading of a word. Tamanhos tpicos so: Character (1 byte)

Half word (16 bits) Word (32 bits) Single Precision Floating Point (1 Word) Double Precision Floating Point (2 Words) Inteiros so representados em complemento de dois. Floating point, em geral, usa o padro IEEE 754. Algumas linguagens (como COBOL) usam packed decimal. MC542 A-1.28 RISC vs CISC RISC = Reduced Instruction Set Computer Conjunto de Instrues pequeno Instrues de tamanho fixo Operaes executadas somente em registradores Chip simples, em geral, executam com velocidade de clock elevada. CISC = Complex Instruction Set Computer Conjunto de Instrues grande Instrues Complexas e de tamanho varivel Operaes Memria-Memria MC542 A-1.29 Projeto CISC premissas Conjunto de Instrues farto pode simplificar o compilador. Conjunto de Instrues farto pode aliviar o

software. Conjunto de Instrues farto pode dar qualidade a arquitetura. Se o tempo de execuo for proporcional ao tamanho do programa, tcnicas de arquitetura que levem a programas menores tambm levam a computadores mais rpidos. MC542 A-1.30 Projeto RISC premissas As funes devem ser simples, a menos que haja uma razo muito forte em contrrio. Decodificao simples e execuo pipelined so mais importantes que o tamanho do programa. Tecnologias de compiladores podem ser usadas para simplificar as instrues ao invs de produzirem instrues complexas. MC542 A-1.31 Codificao do conjunto de Instrues codificao de um RISC tpico instrues de tamanho fixo (32-bit) (3 formatos) 32 32-bit general-purpose registers (R0 contains zero, nmeros de preciso dupla usam dois registradores) Modo de endereamento simples para load/store: base + displacement

(sem indireo) Desvios condicionais simples Delayed branch para evitar penalidade no pipeline Exemplos: DLX, SPARC, MIPS, HP PA-RISC, DEC Alpha, IBM/Motorola PowerPC, Motorola M88000 MC542 A-1.32 Codificao do conjunto de Instrues codificao de um RISC tpico 3 formatos - MIPS 31 R-type I-type J-type 26 21 16 11 6 0 op rs

rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate/address 6 bits 5 bits 5 bits

16 bits op target address 6 bits 26 bits MC542 A-1.33 Arquitetura MIPS Organizao Acesso memria alinhado a: Byte dados Word instrues 0 1 2 3 4 5 6 ... 0 4 8 12

8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 32 bits of data 32 bits of data 32 bits of data 32 bits of data MC542 A-1.34 Arquitetura MIPS Organizao Palavras de 32 bits 3 formatos de instrues R op rs rt rd I op

rs rt 16 bit address J op shamt funct 26 bit address MC542 A-1.35 Arquitetura MIPS Organizao Cdigo C: A[300] = h + A[300]; Cdigo MIPS: lw $t0, 1200($t1) add $t0, $s2, $t0 sw $t0, 1200($t1) op rs

rt 35 9 8 0 43 18 8 9 8 rd address/shamt address/funct 1200 8 0 32 1200 MC542 A-1.36 Conjunto de Registradores MIPS

Name $0 Register Number 0 Usage the constant value 0 $at 1 assembler temporary $v0-$v1 2-3 procedure return values $a0-$a3 4-7 procedure arguments $t0-$t7 $s0-$s7 $t8-$t9

$k0-$k1 $gp $sp $fp $ra 8-15 16-23 24-25 26-27 28 29 30 31 temporaries saved variables more temporaries OS temporaries global pointer stack pointer frame pointer procedure return address MC542 A-1.37 Arquitetura MIPS Organizao 1. Immediate addressing op

rs rt Immediate 2. Register addressing op rs rt rd ... funct Registers Register 3. Base addressing op rs rt Memory Address +

Register Byte Halfword Word 4. PC-relative addressing op rs rt Memory Address PC + Word 5. Pseudodirect addressing op Address PC Memory

Word MC542 A-1.38 Instrues MIPS Soma High-level code a = b + c; MIPS assembly code add a, b, c add: mneumnico, indica qual a operao a ser executada b, c: operandos fonte a : operando destino, aonde ser armazenado o resultado MC542 A-1.39 Instrues MIPS Subtrao High-level code a = b - c; MIPS assembly code sub a, b, c sub : mneumnico, indica qual a operao a ser executada

b, c: operandos fonte a : operando destino, aonde ser armazenado o resultado MC542 A-1.40 Instrues MIPS Cdigo mais complexo: High-level code a = b + c - d; // single line comment /* multiple line comment */ MIPS assembly code add t, b, c # t = b + c sub a, t, d # a = t - d MC542 A-1.41 Instrues MIPS Operandos Um computador necessita de localizaes fsicas de onde buscar os operandos binrios. Um computer busca operandos de: Registradores Memria Constantes (tambm denominados de imediatos) MC542 A-1.42

Instrues MIPS Operandos Memria lenta. Muitas arquiteturas possuem um conjunto pequeno de registradores (rpidos). MIPS tem trinta e dois registradores de 32-bit. MIPS chamado de arquitetura de 32-bit devido seus operandos serem dados de 32-bit. (Uma verso MIPS de 64-bit tambm existe.) MC542 A-1.43 Conjunto de registradores MIPS Name $0 Register Number 0 Usage the constant value 0 $at 1 assembler temporary $v0-$v1

2-3 procedure return values $a0-$a3 4-7 procedure arguments $t0-$t7 $s0-$s7 $t8-$t9 $k0-$k1 $gp $sp $fp $ra 8-15 16-23 24-25 26-27 28 29 30 31 temporaries saved variables more temporaries OS temporaries

global pointer stack pointer frame pointer procedure return address MC542 A-1.44 Instrues MIPS Com os Registradores High-level code MIPS assembly code # $s0 = a, $s1 = b, $s2 = c a = b + c; add $s0, $s1, $s2 MC542 A-1.45 Instrues MIPS Operandos em Memria word-addressable memory Word Address Data 00000003

4 0 F 3 0 7 8 8 Word 3 00000002 0 1 E E 2 8 4 2 Word 2 00000001 F 2 F 1 A C 0 7 Word 1 00000000 A B C D E F 7 8 Word 0 MC542 A-1.46 Instrues MIPS Lendo uma word-addressable memory Assembly code lw $s3, 1($0) # read memory word 1 into $s3 # Load Word Word Address Data 00000003 4 0 F 3 0 7 8 8 Word 3

00000002 0 1 E E 2 8 4 2 Word 2 00000001 F 2 F 1 A C 0 7 Word 1 00000000 A B C D E F 7 8 Word 0 MC542 A-1.47 Instrues MIPS Escrevendo uma word-addressable memory Assembly code Sw $t4, 0x7($0) # write $t4 to memory word 7 # Store Word Word Address Data 00000003 4 0 F 3 0 7 8 8 Word 3 00000002 0 1 E E 2 8 4 2 Word 2 00000001

F 2 F 1 A C 0 7 Word 1 00000000 A B C D E F 7 8 Word 0 MC542 A-1.48 Instrues MIPS Operandos em Memria byte-addressable memory Load e store um nico bytes: load byte (lb) e store byte (sb) Cada word de 32-bit tem 4 bytes, assim o endereo deve ser incrementado de 4 Word Address Data 0000000C 4 0 F 3 0 7 8 8 Word 3 00000008 0 1 E E 2 8 4 2 Word 2 00000004 F 2 F 1 A C 0 7 Word 1 00000000

A B C D E F 7 8 Word 0 width = 4 bytes MC542 A-1.49 Instrues MIPS Lendo uma byte-addressable memory MIPS assembly code lw $s3, 4($0) # read memory word 1 into $s3 Word Address Data 0000000C 4 0 F 3 0 7 8 8 Word 3 00000008 0 1 E E 2 8 4 2 Word 2 00000004 F 2 F 1 A C 0 7 Word 1 00000000 A B C D E F 7 8 Word 0 width = 4 bytes MC542

A-1.50 Instrues MIPS Escrevendo uma byte-addressable memory MIPS assembly code sw $t7, 44($0) # write $t7 into memory word 11 Word Address Data 0000000C 4 0 F 3 0 7 8 8 Word 3 00000008 0 1 E E 2 8 4 2 Word 2 00000004 F 2 F 1 A C 0 7 Word 1 00000000 A B C D E F 7 8 Word 0 width = 4 bytes MC542 A-1.51 Instrues MIPS

Big-Endian e Little-Endian Como so numerados os bytes na word Big-Endian Little-Endian Byte Address Word Address C D E F C F 8 9 A B 8 B A 9 8 4

5 6 7 4 7 6 5 4 0 1 2 3 0 3 2 1 0

MSB LSB Byte Address MSB E D C LSB MC542 A-1.52 Instrues MIPS Big- e Little-Endian Exemplos: Suponha que inicialmente $t0 contm 0x23456789. Aps o seguinte trecho de programa ser executado em um sistema bigendian, qual o valor de $s0. E em um sistema little-endian? sw $t0, 0($0) lb $s0, 1($0) MC542 A-1.53 Instrues MIPS Big- e Little-Endian Exemplos: Suponha que inicialmente $t0 contm 0x23456789. Aps o seguinte trecho de programa ser executado em um sistema big-endian, qual o valor de $s0. E em um sistema little-endian?

sw $t0, 0($0) lb $s0, 1($0) Big-endian: 0x00000045 Little-endian: 0x00000067 Big-Endian Byte Address 0 1 2 3 Data Value 23 45 67 89 MSB LSB Little-Endian Word Address 0 3 2 1 0 Byte Address 23 45 67 89 Data Value MSB LSB MC542 A-1.54 Instrues MIPS Operandos: Constantes/Imediatos

Um imediato um nmero de 16-bit em complemento de dois. High-level code a = a + 4; b = a 12; MIPS assembly # $s0 = a, $s1 addi $s0, $s0, addi $s1, $s0, code = b 4 -12 MC542 A-1.55 Instrues MIPS Linguagem de Mquina Computadores s conhecem 1s e 0s Linguagem de Mquina: representao binria das instrues Instrues de 32-bit Simplicidade em favor da regularidade: dados e instrues de de 32-bit Trs formatos de instrues : R-Type: register operands I-Type: immediate operand

J-Type: para jump MC542 A-1.56 Instrues MIPS R-type: Register-type 3 operandos registradores: rs, rt: source registers rd: destination register Outros campos: op: cdigo da operao ou opcode funct: funo juntos, o opcode e a funo informam a operao a ser executada shamt: a quantidade de shift para instrues de deslocamento R-Type op 6 bits rs 5 bits rt rd

shamt funct 5 bits 5 bits 5 bits 6 bits MC542 A-1.57 Instrues MIPS Field Values Assembly Code rs op rt rd shamt funct add $s0, $s1, $s2 0

17 18 16 0 32 sub $t0, $t3, $t5 0 11 13 8 0 34 5 bits 5 bits 5 bits 5 bits 6 bits

6 bits Machine Code op rs rt rd shamt funct 000000 10001 10010 10000 00000 100000 (0x02328020) 000000 01011 01101 01000 00000 100010 (0x016D4022) 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Nota: a ordem dos registradores no cdigo assembly: add rd, rs, rt MC542

A-1.58 Instrues MIPS I-Type: Immediate-Type 3 operands: rs, rt: register operands imm: 16-bit em complemento de dois immediate Outros campos: op: opcode I-Type op 6 bits rs 5 bits rt imm 5 bits 16 bits MC542 A-1.59 Instrues MIPS Exemplo I-Type: Assembly Code

Field Values rs op rt imm addi $s0, $s1, 5 8 17 16 5 addi $t0, $s3, -12 8 19 8 -12 lw $t2, 32($0)

35 0 10 32 sw $s1, 43 9 17 4 4($t1) 6 bits Nota: a ordem dos registradores no cdigo assembly: addi rt, rs, imm lw rt, imm(rs) sw

rt, imm(rs) 5 bits 5 bits 16 bits Machine Code op rs rt imm 001000 10001 10000 0000 0000 0000 0101 (0x22300005) 001000 10011 01000 1111 1111 1111 0100 (0x2268FFF4) 100011 00000 01010 0000 0000 0010 0000 (0x8C0A0020) 101011 01001 10001 0000 0000 0000 0100 (0xAD310004) 6 bits 5 bits 5 bits 16 bits MC542 A-1.60 Instrues MIPS J-Type: Jump-Type 26-bit address operand (addr) Usado nas instrues jump (j)

J-Type op addr 6 bits 26 bits MC542 A-1.61 Instrues MIPS Formatos das Instrues R-Type op 6 bits rs 5 bits rt rd shamt funct 5 bits 5 bits

5 bits 6 bits I-Type op 6 bits rs 5 bits rt imm 5 bits 16 bits J-Type op addr 6 bits 26 bits MC542 A-1.62 Programa Armazenado Instrues e dados de 32-bit armazenados na memria Seqncia de instrues: a nica diferena

entre dois programas Execuode um novo programa: Simplismente armazene o novo programa na memria Execuo do programa pelo hardware do processador: fetches (reads) as instrues da memria em seqncia Executa a operao especificada Um program counter (PC) indica a instruo corrente (ou a prxima instruo). no MIPS, programas tipicamente iniciam no endereo de memria 0x00400000. MC542 A-1.63 Programa Armazenado Exemplo: Assembly Code Machine Code lw $t2, 32($0) 0x8C0A0020 add $s0, $s1, $s2

0x02328020 addi $t0, $s3, -12 0x2268FFF4 sub 0x016D4022 $t0, $t3, $t5 Stored Program Address Instructions 0040000C 0 1 6 D4 0 2 2 00400008 2 2 6 8 F F F 4 00400004 0 2 3 2 8 0 2 0 00400000 8 C0 A0 0 2 0 Main Memory

PC MC542 A-1.64 Interpretando o cdigo de Mquina Inicia com o opcode Opcode informa como fazer o parse dos bits remanecentes se opcode todo 0s R-type instruction Function bits informa qual instruo Caso contrrio opcode informa qual a instruo Machine Code rs op rt Field Values imm op (0x2237FFF1) 001000 10001 10111 1111 1111 1111 0001 2 op 2

3 rs 7 rt F rd F F 2 F 3 shamt funct 4 0 2 8 rt 17

Assembly Code imm 23 -15 addi $s7, $s1, -15 1 rs op (0x02F34022) 000000 10111 10011 01000 00000 100010 0 rs 0 rt 23 rd 19 shamt funct 8

0 34 sub $t0, $s7, $s3 2 MC542 A-1.65 Instrues Lgicas and, or, xor, nor and: til para mascar de bits Estrando o byte menos significativo de uma word: 0xF234012F AND 0xFF = 0x0000002F or: til para combinar bits Combinar 0xF2340000 com 0x000012BC: 0xF2340000 OR 0x000012BC = 0xF23412BC nor: til para inverter bits: A NOR $0 = NOT A andi, ori, xori O imediato de 16-bit zero-extended (no signextended) MC542 A-1.66 Instrues Lgicas Source Registers $s1 1111 1111 1111 1111 0000 0000 0000 0000

$s2 0100 0110 1010 0001 1111 0000 1011 0111 Assembly Code Result and $s3, $s1, $s2 $s3 0100 0110 1010 0001 0000 0000 0000 0000 or $s4, $s1, $s2 $s4 1111 1111 1111 1111 1111 0000 1011 0111 xor $s5, $s1, $s2 $s5 1011 1001 0101 1110 1111 0000 1011 0111 nor $s6, $s1, $s2 $s6 0000 0000 0000 0000 0000 1111 0100 1000 MC542 A-1.67 Instrues Lgicas Source Values $s1 0000 0000 0000 0000 0000 0000 1111 1111 imm 0000 0000 0000 0000 1111 1010 0011 0100 zero-extended Assembly Code

Result andi $s2, $s1, 0xFA34 $s2 0000 0000 0000 0000 0000 0000 0011 0100 ori $s3, $s1, 0xFA34 $s3 0000 0000 0000 0000 1111 1010 1111 1111 xori $s4, $s1, 0xFA34 $s4 0000 0000 0000 0000 1111 1010 1100 1011 MC542 A-1.68 Instrues Shift sll: shift left logical Exemplo: sll $t0, $t1, 5 # $t0 <= $t1 << 5 srl: shift right logical Exemplo : srl $t0, $t1, 5 # $t0 <= $t1 >> 5 sra: shift right arithmetic Exemplo : sra $t0, $t1, 5 # $t0 <= $t1 >>> 5 Variable shift instructions: sllv: shift left logical variable Exemplo : sll $t0, $t1, $t2 # $t0 <= $t1 << $t2 srlv: shift right logical variable Exemplo : srl $t0, $t1, $t2 # $t0 <= $t1 >> $t2 srav: shift right arithmetic variable Exemplo : sra $t0, $t1, $t2 # $t0 <= $t1 >>> $t2 MC542 A-1.69 Instrues Shift Assembly Code

Field Values op rs rt rd shamt funct sll $t0, $s1, 2 0 0 17 8 2 0 srl $s2, $s1, 2 0 0 17

18 2 2 sra $s3, $s1, 2 0 0 17 19 2 3 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Machine Code

op rs rt rd shamt funct 000000 00000 10001 01000 00010 000000 (0x00114080) 000000 00000 10001 10010 00010 000010 (0x00119082) 000000 00000 10001 10011 00010 000011 (0x00119883) 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits MC542 A-1.70 Gerando Constantes Constantes de 16-bit usando addi: High-level code // int is a 32-bit signed word int a = 0x4f3c;

MIPS assembly code # $s0 = a addi $s0, $0, 0x4f3c Constantes de 32-bit usando load upper immediate (lui) e ori: (lui loads o imediato de 16-bit na metade mais significativa do registrador seta a menos significativa com 0.) High-level code int a = 0xFEDC8765; MIPS assembly code # $s0 = a lui $s0, 0xFEDC ori $s0, $s0, 0x8765 MC542 A-1.71 Multiplicao e Diviso Registradores especiais: lo, hi Multiplicao 32 32 bit, resultado de 64 bit mult $s0, $s1 Resultado em hi, lo Diviso 32-bit, quociente de 32-bit, resto de 32-bit div $s0, $s1 Quociente em lo Resto em hi

MC542 A-1.72 Desvios Todo programa executa instrues for a da seqncia. Tipos de desvios (branches): Conditional branches: branch if equal (beq) branch if not equal (bne) Unconditional branches: jump (j) jump register (jr) jump and link (jal) MC542 A-1.73 Beq: exemplo # MIPS assembly addi addi sll beq addi sub $s0, $s1, $s1, $s0, $s1,

$s1, $0, 4 $0, 1 $s1, 2 $s1, target $s1, 1 $s1, $s0 target: add $s1, $s1, $s0 # # # # # # $s0 = 0 + 4 = 4 $s1 = 0 + 1 = 1 $s1 = 1 << 2 = 4 branch is taken not executed not executed # label # $s1 = 4 + 4 = 8 MC542 A-1.74 Bne: exemplo

# MIPS assembly addi addi sll bne addi sub target: add $s0, $s1, $s1, $s0, $s1, $s1, $0, 4 $0, 1 $s1, 2 $s1, target $s1, 1 $s1, $s0 $s1, $s1, $s0 # # # # # # $s0 = 0 + 4 = 4

$s1 = 0 + 1 = 1 $s1 = 1 << 2 = 4 branch not taken $s1 = 4 + 1 = 5 $s1 = 5 4 = 1 # $s1 = 1 + 4 = 5 MC542 A-1.75 Desvio incondicional (j) # MIPS assembly addi $s0, $0, 4 addi $s1, $0, 1 j target sra $s1, $s1, 2 addi $s1, $s1, 1 sub $s1, $s1, $s0 # $s0 = 4 # $s1 = 1 # jump to target # not executed # not executed # not executed target: add # $s1 = 1 + 4 = 5

$s1, $s1, $s0 MC542 A-1.76 Desvio incondicional (jr) # MIPS assembly 0x00002000 0x00002004 0x00002008 0x0000200C 0x00002010 addi jr addi sra lw $s0, $0, 0x2010 $s0 $s1, $0, 1 $s1, $s1, 2 $s3, 44($s1) MC542 A-1.77 Construes de Alto Nvel if statements if/else statements while loops for loops

MC542 A-1.78 If Statement High-level code if (i == j) f = g + h; MIPS assembly code # $s0 = f, $s1 = g, $s2 = h # $s3 = i, $s4 = j bne $s3, $s4, L1 add $s0, $s1, $s2 f = f i; L1: sub $s0, $s0, $s3 Note que em assembly o teste o oposto (i != j) do teste em alto nvel (i == j). MC542 A-1.79 If / Else Statement High-level code if (i == j) f = g + h; else

f = f i; MIPS assembly # $s0 = f, $s1 # $s3 = i, $s4 bne $s3, add $s0, j done L1: sub $s0, done: code = g, $s2 = h = j $s4, L1 $s1, $s2 $s0, $s3 MC542 A-1.80 While Loops High-level code // determines the power // of x such that 2x = 128 int pow = 1; int x = 0; while (pow != 128) { pow = pow * 2; x = x + 1; }

MIPS assembly code # $s0 = pow, $s1 = x addi add addi while: beq sll addi j done: $s0, $0, 1 $s1, $0, $0 $t0, $0, 128 $s0, $t0, done $s0, $s0, 1 $s1, $s1, 1 while MC542 A-1.81 For Loops A forma geral de um for loop : for (inicializao; condio; loop) corpo do loop inicializao: executado antes do loop

condio: testada no inicio de cada iterao loop: executa no fim de cada iterao Corpodo loop: executado para cada vez que a condio satisfeita MC542 A-1.82 For Loops High-level code MIPS assembly code // add the numbers from 0 to 9 # $s0 = i, $s1 = sum int sum = 0; addi $s1, $0, 0 int i; add $s0, $0, $0 addi $t0, $0, 10 for (i=0; i!=10; i = i+1) { for: beq $s0, $t0, done sum = sum + i; add $s1, $s1, $s0 } addi $s0, $s0, 1 j for done: MC542 A-1.83 For Loops: Usando slt High-level code

// add the powers of 2 from 1 // to 100 int sum = 0; int i; for (i=1; i < 101; i = i*2) { sum = sum + i; } MIPS assembly code # $s0 = i, $s1 = sum addi $s1, $0, 0 addi $s0, $0, 1 addi $t0, $0, 101 loop: slt $t1, $s0,$t0 beq $t1, $0, done add $s1, $s1, $s0 sll $s0, $s0, 1 j loop done: $t1 = 1 if i < 101. MC542 A-1.84 Arrays Utilizado para acesso a uma grande quantidade de dados similares Elemento do Array: acesso por meio de um indice Tamanho do Array: nmero de elementos no array MC542

A-1.85 Array: exemplo Array com 5 elementos Endereo base = 0x12348000 (endereo do primeiro elemento, array[0]) Primeiro passo para acesso a um array: carregar o endereo base em um registrador 0x12340010 0x1234800C 0x12348008 0x12348004 0x12348000 array[4] array[3] array[2] array[1] array[0] MC542 A-1.86 Array // high-level code int array[5]; array[0] = array[0] * 2; array[1] = array[1] * 2; # MIPS assembly code # array base address = $s0 lui $s0, 0x1234 # put 0x1234 in upper half of $S0 ori $s0, $s0, 0x8000

# put 0x8000 in lower half of $s0 lw $t1, 0($s0) sll $t1, $t1, 1 sw $t1, 0($s0) # $t1 = array[0] # $t1 = $t1 * 2 # array[0] = $t1 lw $t1, 4($s0) sll $t1, $t1, 1 sw $t1, 4($s0) # $t1 = array[1] # $t1 = $t1 * 2 # array[1] = $t1 MC542 A-1.87 Array Usando For // high-level code int array[1000]; int i; for (i=0; i < 1000; i = i + 1) array[i] = array[i] * 8; MC542 A-1.88 Array Usando For # MIPS assembly code # $s0 = array base address, # initialization code lui $s0, 0x23B8

# ori $s0, $s0, 0xF000 # addi $s1, $0, 0 # addi $t2, $0, 1000 # loop: slt beq sll add lw sll sw addi j done: $t0, $t0, $t0, $t0, $t1, $t1, $t1, $s1, loop $s1, $t2 $0, done $s1, 2 $t0, $s0 0($t0)

$t1, 3 0($t0) $s1, 1 # # # # # # # # # $s1 = i $s0 $s0 i = $t2 = 0x23B80000 = 0x23B8F000 0 = 1000 i < 1000? if not then done $t0 = i * 4 (byte offset) address of array[i] $t1 = array[i] $t1 = array[i] * 8 array[i] = array[i] * 8 i = i + 1 repeat

MC542 A-1.89 Chamada de Procedimento High-level code void main() { int y; y = sum(42, 7); ... } int sum(int a, int b) { return (a + b); } MC542 A-1.90 Chamada de Procedimento Chamada de Procedimento - convenes: Chamada: Passa argumentos para o procedimento. Procedimento: No deve sobre-escrever os registradores nem a memria usados por quem chama Retorna ao ponto de chamada Retorna o resultado para quem chama Convenes MIPS:

Chamada de procedimento: jump e link (jal) Retorno de procedimento: jump register (jr) Argumentos: $a0 - $a3 Retorno do valor calculado: $v0 MC542 A-1.91 Chamada de Procedimento High-level code int main() { simple(); a = b + c; } MIPS assembly code void simple() { return; } 0x00401020 simple: jr $ra 0x00400200 main: jal 0x00400204 add ... simple $s0, $s1, $s2 MC542

A-1.92 Chamada de Procedimento High-level code int main() { simple(); a = b + c; } MIPS assembly code void simple() { return; } 0x00401020 simple: jr $ra 0x00400200 main: jal 0x00400204 add ... simple $s0, $s1, $s2 jal: salta para simple e salva PC+4 no registrador de endereo de retorno ($ra), neste caso, $ra = 0x00400204 aps jal ser executado. jr $ra: salta para o endereo em $ra, neste caso 0x00400204. MC542 A-1.93 Argumentos e Retorno de Valores Conveno MIPS c: Argumentos: $a0 - $a3

Retorno: $v0 MC542 A-1.94 Argumentos e Retorno de Valores High-level code int main() { int y; ... y = diffofsums(2, 3, 4, 5); ... } // 4 arguments int diffofsums(int f, int g, int h, int i) { int result; result = (f + g) - (h + i); return result; // return value } MC542 A-1.95 Argumentos e Retorno de Valores Cdigo MIPS (assembly) # $s0 = y main: ... addi $a0, $0, 2 # argument 0 = 2

addi $a1, $0, 3 # argument 1 = 3 addi $a2, $0, 4 # argument 2 = 4 addi $a3, $0, 5 # argument 3 = 5 jal diffofsums # call procedure add $s0, $v0, $0 # y = returned value ... # $s0 = result diffofsums: add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller MC542 A-1.96 Argumentos e Retorno de Valores Cdigo MIPS (assembly) # $s0 = result diffofsums: add $t0, $a0, $a1 # $t0 = f + g add $t1, $a2, $a3 # $t1 = h + i sub $s0, $t0, $t1 # result = (f + g) - (h + i) add $v0, $s0, $0 # put return value in $v0 jr $ra # return to caller diffofsums sobre-escreve 3 registradores: $t0, $t1, e $s0 diffofsums pode usar a pilha para armazenar temporariamente os registradores MC542 A-1.97

Pilha Cresce para baixo (dos endereos maiores para os menores) Stack pointer: $sp, aponta para o topo da pilha Address Data Address Data 7FFFFFFC 12345678 7FFFFFFC 12345678 7FFFFFF8 7FFFFFF8 AABBCCDD 7FFFFFF4 7FFFFFF4 11223344 7FFFFFF0

7FFFFFF0 $sp $sp MC542 A-1.98 Chamada de Procedimentos Usando a Pilha O procedimento chamado no deve provocar nenhum efeito colateral. Ms diffofsums sobre-escreve 3 registradores: $t0, $t1, $s0 # MIPS assembly # $s0 = result diffofsums: add $t0, $a0, add $t1, $a2, sub $s0, $t0, add $v0, $s0, jr $ra $a1 $a3 $t1 $0 # # # #

# $t0 = f + g $t1 = h + i result = (f + g) - (h + i) put return value in $v0 return to caller MC542 A-1.99 Chamada de Procedimentos Usando a Pilha # $s0 = result diffofsums: addi $sp, $sp, -12 sw sw sw add add sub add lw lw lw addi jr $s0, $t0, $t1, $t0, $t1,

$s0, $v0, $t1, $t0, $s0, $sp, $ra 8($sp) 4($sp) 0($sp) $a0, $a1 $a2, $a3 $t0, $t1 $s0, $0 0($sp) 4($sp) 8($sp) $sp, 12 # # # # # # # # # # # # # #

make space on stack to store 3 registers save $s0 on stack save $t0 on stack save $t1 on stack $t0 = f + g $t1 = h + i result = (f + g) - (h + i) put return value in $v0 restore $t1 from stack restore $t0 from stack restore $s0 from stack deallocate stack space return to caller MC542 A-1.100 A Pilha durante a Chamada de diffofsums FC F8 F4 F0 (a) ? Address Data $sp stack frame Address Data

Address Data FC ? FC F8 $s0 F8 F4 $t0 F4 F0 $t1 (b) $sp ? $sp F0

(c) MC542 A-1.101 Registradores Preserved Nonpreserved Callee-Saved $s0 - $s7 Caller-Saved $t0 - $t9 $ra $a0 - $a3 $sp $v0 - $v1 stack above $sp stack below $sp MC542 A-1.102 Chamadas Mltiplas de Procedimentos

proc1: addi $sp, $sp, -4 sw $ra, 0($sp) jal proc2 ... lw $ra, 0($sp) addi $sp, $sp, 4 jr $ra # make space on stack # save $ra on stack # restore $r0 from stack # deallocate stack space # return to caller MC542 A-1.103 Armazenando Registradores na Pilha # $s0 = result diffofsums: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $0 lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra

# # # # # # # # # # make space on stack to store one register save $s0 on stack $t0 = f + g $t1 = h + i result = (f + g) - (h + i) put return value in $v0 restore $s0 from stack deallocate stack space return to caller MC542 A-1.104 Chamada Recursiva de Procedimentos High-level code int factorial(int n) { if (n <= 1) return 1; else return (n * factorial(n-1)); }

MC542 A-1.105 Chamada Recursiva de Procedimentos MIPS assembly code 0x90 factorial: addi $sp, $sp, -8 # make room 0x94 sw $a0, 4($sp) # store $a0 0x98 sw $ra, 0($sp) # store $ra 0x9C addi $t0, $0, 2 0xA0 slt $t0, $a0, $t0 # a <= 1 ? 0xA4 beq $t0, $0, else # no: go to else 0xA8 addi $v0, $0, 1 # yes: return 1 0xAC addi $sp, $sp, 8 # restore $sp 0xB0 jr $ra # return 0xB4 else: addi $a0, $a0, -1 # n = n - 1 0xB8 jal factorial # recursive call 0xBC lw $ra, 0($sp) # restore $ra

0xC0 lw $a0, 4($sp) # restore $a0 0xC4 addi $sp, $sp, 8 # restore $sp 0xC8 mul $v0, $a0, $v0 # n * factorial(n-1) 0xCC jr $ra # return MC542 A-1.106 A Pilha Durante a Chamada Recursiva Address Data FC Address Data $sp FC Address Data $sp FC F8 F8 $a0 (0x3)

F4 F4 $ra F0 F0 $a0 (0x2) EC EC $ra (0xBC) E8 E8 $a0 (0x1) E4 E4 $ra (0xBC) E0 E0

E0 DC DC DC $sp $sp $sp F8 $a0 (0x3) F4 $ra F0 $a0 (0x2) EC $ra (0xBC) E8 $a0 (0x1) E4

$ra (0xBC) $sp $v0 = 6 $sp $a0 = 3 $v0 = 3 x 2 $sp $a0 = 2 $v0 = 2 x 1 $sp $a0 = 1 $v0 = 1 x 1 MC542 A-1.107 Modos de Endereamento Como endereamos os operandos? Register Immediate

Base Addressing PC-Relative Pseudo Direct MC542 A-1.108 Modos de Endereamento Register Os Operandos esto somente em Registradores Exemplo: add $s0, $t2, $t3 Exemplo: sub $t8, $s1, $0 Immediate Addressing Imediato de 16-bit usado como operando Exemplo: addi $s4, $t5, -73 Exemplo: ori $t3, $t7, 0xFF MC542 A-1.109 Modos de Endereamento Base Addressing O endereo do operando : base address + sign-extended immediate Exemplo: lw $s4, 72($0) Address = $0 + 72 Exemplo: sw

$t2, -25($t1) Address = $t1 - 25 MC542 A-1.110 Modos de Endereamento PC-Relative Addressing 0x10 0x14 0x18 0x1C 0x20 0x24 else: beq addi addi jr addi jal $t0, $0, else $v0, $0, 1 $sp, $sp, i $ra $a0, $a0, -1 factorial Assembly Code

Field Values op beq $t0, $0, else (beq $t0, $0, 3) rs 4 6 bits rt 8 5 bits imm 0 5 bits 3 5 bits 5 bits 6 bits MC542 A-1.111 Modos de Endereamento

Pseudo-direct Addressing 0x0040005C ... 0x004000A0 sum: jal sum add $v0, $a0, $a1 JTA 0000 0000 0100 0000 0000 0000 1010 0000 (0x004000A0) 26-bit addr 0000 0000 0100 0000 0000 0000 1010 0000 (0x0100028) 0 1 0 0 imm 3 6 bits op 0x0100028 26 bits

2 8 Machine Code Field Values op 0 addr 000011 00 0001 0000 0000 0000 0010 1000 (0x0C100028) 6 bits 26 bits MC542 A-1.112 Como Executar uma Aplicao High Level Code Compiler Assembly Code Assembler Object File Object Files Library Files Linker Executable

Loader Memory MC542 A-1.113 O que Deve ser Armazenado na Memria Instrues (tambm chamado: text) Dado Global/sttico: alocado antes de comear a execuo Dinmico: alocado pelo programa em execuo Qual o tamanho da memria? No mximo 232 = 4 gigabytes (4 GB) Apartir do endereo 0x00000000 ao 0xFFFFFFFF MC542 A-1.114 Mapa de Memria MIPS Address Segment 0xFFFFFFFC Reserved 0x80000000 0x7FFFFFFC Stack Dynamic Data 0x10010000 0x1000FFFC

Heap Static Data 0x10000000 0x0FFFFFFC Text 0x00400000 0x003FFFFC Reserved 0x00000000 MC542 A-1.115 Executando um Programa High Level Code Compiler Assembly Code Assembler Object File Object Files Library Files Linker Executable Loader Memory MC542 A-1.116

Exemplo: Programa em C int f, g, y; int { f g y // global variables main(void) = 2; = 3; = sum(f, g); return y; } int sum(int a, int b) { return (a + b); } MC542 A-1.117 Exemplo: Programa em Assembly int f, g, y; // global int main(void) { f = 2; g = 3; y = sum(f, g);

return y; } int sum(int a, int b) { return (a + b); } .data f: g: y: .text main: addi sw addi sw addi sw jal sw lw addi jr sum: add jr $sp, $ra, $a0, $a0, $a1, $a1, sum

$v0, $ra, $sp, $ra $sp, -4 0($sp) $0, 2 f $0, 3 g y 0($sp) $sp, 4 $v0, $a0, $a1 $ra # # # # # # # # # # # stack frame store $ra $a0 = 2 f = 2

$a1 = 3 g = 3 call sum y = sum() restore $ra restore $sp return to OS # $v0 = a + b # return MC542 A-1.118 Mapa de Memria MIPS Address Segment 0xFFFFFFFC Reserved 0x80000000 0x7FFFFFFC Stack Dynamic Data 0x10010000 0x1000FFFC Heap Static Data 0x10000000

0x0FFFFFFC Text 0x00400000 0x003FFFFC Reserved 0x00000000 MC542 A-1.119 Exemplo: Tabela de Smbolos Symbol Address f 0x10000000 g 0x10000004 y 0x10000008 main 0x00400000

sum 0x0040002C MC542 A-1.120 Exemplo: Programa Executvel Executable file header Text segment Data segment Text Size Data Size 0x34 (52 bytes) 0xC (12 bytes) Address Instruction 0x00400000 0x23BDFFFC addi $sp, $sp, -4 0x00400004

0xAFBF0000 sw 0x00400008 0x20040002 addi $a0, $0, 2 0x0040000C 0xAF848000 sw 0x00400010 0x20050003 addi $a1, $0, 3 0x00400014 0xAF858004 sw $a1, 0x8004 ($gp) 0x00400018 0x0C10000B

jal 0x0040002C 0x0040001C 0xAF828008 sw $v0, 0x8008 ($gp) 0x00400020 0x8FBF0000 lw $ra, 0 ($sp) 0x00400024 0x23BD0004 addi $sp, $sp, -4 0x00400028 0x03E00008 jr 0x0040002C

0x00851020 add $v0, $a0, $a1 0x00400030 0x03E0008 jr Address Data 0x10000000 f 0x10000004 g 0x10000008 y $ra, 0 ($sp) $a0, 0x8000 ($gp) $ra $ra MC542 A-1.121

Exemplo: Programa na Memria Address Memory Reserved 0x7FFFFFFC Stack 0x10010000 Heap $sp = 0x7FFFFFFC $gp = 0x10008000 y g 0x10000000 f 0x03E00008 0x00851020 0x03E00008 0x23BD0004 0x8FBF0000 0xAF828008 0x0C10000B 0xAF858004 0x20050003 0xAF848000

0x20040002 0xAFBF0000 0x00400000 0x23BDFFFC PC = 0x00400000 Reserved MC542 A-1.122 Pseudo Instrues Pseudoinstruction MIPS Instructions li $s0, 0x1234AA77 lui $s0, 0x1234 ori $s0, 0xAA77 mul $s0, $s1, $s2 mult $s1, $s2 mflo $s0 clear $t0 add $t0, $0, $0 move $s1, $s2

add $s2, $s1, $0 nop sll $0, $0, 0 MC542 A-1.123 Excees (Interrupes) Chamada de procedimento, no prevista no cdigo, para um exception handler Causado por: Hardware, tambm chamodo interrupo, exemp: keyboard Software, tambm chamado de traps, exemp.: instruo indefinida Quando uma exceo ocorre, o processador: Registra a causa da exceo Desvia a execuo para exception handler no endereo de instruo 0x80000180 Retorna ao programa MC542 A-1.124 Registradores de Exceo No faz parte do register file. Cause Registra a causa da exceo EPC (Exception PC) Registra o PC onde ocorreu a exceo

EPC e Cause: parte do Coprocessador 0 Move from Coprocessor 0 mfc0 $t0, EPC Move o contedo de EPC para $t0 MC542 A-1.125 Excees Exception Cause Hardware Interrupt 0x00000000 System Call 0x00000020 Breakpoint / Divide by 0 0x00000024 Undefined Instruction 0x00000028 Arithmetic Overflow 0x00000030

MC542 A-1.126 Excees O Processador salva a causa e o PC em Cause e EPC Processador desvia para o exception handler (0x80000180) Exception handler: Salva os registradores na pilha L o registrador Cause mfc0 Cause, $t0 Trata a exceo Restaura os registradores Retorna ao programa mfc0 EPC, $k0 jr $k0 MC542 A-1.127 Instrues signed e Unsigned Soma e Subtrao Multiplicao e Diviso Set less than MC542 A-1.128 Instrues Soma e subtrao Signed: add, addi, sub Executa a mesma operao que a verso unsigned

Porm o processador gera exceo se overflow Unsigned: addu, addiu, subu O processador no gera exceo se overflow Nota: addiu sign-extends o imediato Multiplicao e Diviso Signed: mult, div Unsigned: multu, divu Set Less Than Signed: slt, slti Unsigned: sltu, sltiu Nota: sltiu sign-extends o imediato antes da comparao MC542 A-1.129 Instrues Loads Signed: Sign-extends para criar o valor de 32-bit Load halfword: lh Load byte: lb Unsigned: addu, addiu, subu Zero-extends para criar o valor de 32-bit Load halfword unsigned: lhu Load byte: lbu MC542 A-1.130 Ponto-Flutuante Floating-point coprocessor (Coprocessor 1) 32 registradores de 32-bit ($f0 - $f31)

Valores Double-precision so mantidos em dois floating point registers e.g., $f0 e $f1, $f2 e $f3, etc. Assim, os registradores double-precision floating point so: $f0, $f2, $f4, etc. MC542 A-1.131 Ponto-Flutuante Name Register Number Usage $fv0 - $fv1 0, 2 return values $ft0 - $ft3 4, 6, 8, 10 temporary variables $fa0 - $fa1 12, 14 procedure arguments

$ft4 - $ft8 16, 18 temporary variables $fs0 - $fs5 20, 22, 24, 26, 28, 30 saved variables MC542 A-1.132

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