Optimality Study of Logic Synthesis for LUT-Based FPGAs

Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication Speaker: Peipei Zhou Student: Peipei Zhou, Hyunseok Park, Zhenman Fang, Faculty: Jason Cong, Andre DeHon II = 1 or not? # Publications Related Work by Year 10 8 6 4 2 0 2010

2011 2012 2013 2014 2015 Year # Publications Related Work by Conference 12 8 4 0

FPGA FCCM FPT Conference FPL 2 A new Question, II vs Energy and II > 1 # Publications Related Work by Target II 40 35

30 25 20 15 10 5 0 II=1 II1 3 A case study of MM II change, what happens? 4

Architecture for II = 1, II = N a[0][0] a[0][0] b[1][0] b[0][0] b[1][1] b[0][1] b[1][2] b[0][2] b[1][3] b[0][3]

b[1][4] b[0][4] b[1][5] b[0][5] II = 1 II = N 5 Resource 25000 350 300

20000 250 15000 200 10000 150 100 5000 0 50 1

2 4 8 FF LUT 16 DSP 32 64 0 6

GFLOPS 140 120 100 80 60 40 20 0 1 2 4 8 16

32 64 7 Experimental results Xilinx virtex-7 xc485, Vivado 2015.1.5 Energy(uJ) II 8 Highlight in the poster Logic, DSP, Interconnect, BRAM, leakage Flat compute(logic /dsp), bram Interconnect

interconnect 9 Highlight in the poster 10 Thank you Welcome to My Poster @2:20PM 11