Universal Reconfigurable Processing Platform for Space Presented by
Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC Introduction An increasing number of spacecraft system engineers and scientists are demanding: More processing power Flexible architecture Standard / COTS communication interfaces Multiple Mission Modes / Reconfigurability Small form factor Mission hardware reuse Low power High speed SERDES High Reliability MAPLD 2009 Gordonicus LLC 2 Features No blind and buried vias Flight board meets IPC 6012 Class 3 This hardware platform provides these needs by combining: Reconfigurable State-of-the-Art High Speed Data Processing Capabilities Addition of 1553 A Rad Hard LEON3FT Processor Addition of 100 Mb Ethernet 1 Gbyte protected SDRAM Addition of 200 Mb Spacewire routers Addition of COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2
ex l f o r e A T F 3 N LEO UT699 STS125 Mission MAPLD 2009 Gordonicus LLC 3 LEON3FT Processing Applications Guidance, Navigation and Control (GNC) Control and Data Handling (CDH) Xilinx Monitoring and Reconfiguration MAPLD 2009 Gordonicus LLC 4 Xilinx Processing Applications
High Speed DSP Algorithm Processing Image Processing Pose Estimation Algorithms Communications / Radio Data Encryption / Decryption Waveform Processing Instrument Data Validation and Compression Application Reconfigurable While in Flight MAPLD 2009 Gordonicus LLC 5 SPECIFICATIONS 5 PROCESSORS MEMORY LEON3FT ASIC 1 GByte SDRAM AeroFlex UT699 SPARCTM V8/LEON 3FT Reed Solomon Protected corrects for 2 66 MHz Up to 52.8 MIPS nibble upsets Floating Point and MMU 8 Gbit FLASH TID: 300 krad (Si) stored in two banks SEL Immune >110 MeV-cm2/mg
4 x 350 MHz PowerPC 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) 8 Gbit SDRAM 2Gbits per PPC405 2 MBbyte SRAM Protected (Self Scrubbing) 32 KByte PROM SMALL SIZE DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet port DEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port
JTAG 10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP CONSOLE PORT LEON3FT UART Rate configurable DIMENSIONS FRONT PANEL DEVELOPMENT / DEBUG PORTS STANDARD I/O INTERFACES Standard 3U cPCI Single slot front panel configuration
PPC3 4 Designs = Quad Redundant or Single Strand 2 Designs = 1 Design per Xilinx 1 Design TMRed using both Xilinx MAPLD 2009 Gordonicus LLC 11 Xilinx Reconfiguration WITHOUT disruption to the other nodes Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric. Top Xilinx QV4 FX60 PPC0 PPC1 PPC2 PPC3 SelectMap SDRAM Control Logic FLASH A Singe Node can be reconfigured with PPC Operating system PPC application code or Xilinx fabric reconfiguration Bottom Xilinx QV4 FX60 MAPLD 2009 Gordonicus LLC 12 STANDARD INTERFACES
CompactPCI Console Port Async UART 1553 SpaceWire MAPLD 2009 Gordonicus LLC 13 CompactPCI MIL-STD-1553 A/B LEON3FT Console Port F R MIL-STD-1553 A/B O 1553 A/B N Transceiver T P A N E L Aeroflex UT63M143 AMBA 1553 Core Actel RTAX2000 AMBA Bus Bridge via
LEON Memory Bus READY AMBA BUS 32 Bit 33 MHz CompactPCI LEON3FT AMBA BUS LEON RS422 Console Port MAPLD 2009 Gordonicus LLC 14 SpaceWire Ports 10 Front Panel 200/100/50 Mbps 200Mbps Configurable F R O N T P A N E L SpW Router 5 Port
RTAX 200Mbps SpW Router 5 Port LEON3FT 200Mbps Xilinx 200Mbps Configurable Front Panel Conn. Thru-hole Jumpers 2 Backplane via Jumpers MAPLD 2009 Gordonicus LLC 4 Backplane C P C I P 2 15 Configurable I/O What if my instrument interface is not SpaceWire? What if I need a custom interface on the backplane? ie: I2C What if I forgot to add a control line to a device? MAPLD 2009 Gordonicus LLC 16
73 User Defined I/O Sync / Async Serial IF I2C 1 Wire Protocol 12 User Defined I/O ACTEL LVDS OR F R 10 Bi-Dir User Defined O N I/O T P A N E L RS422 LEON3FT 2 GPIO C P C I LVDS OR RS422 LVDS 39 User Defined I/O
OR RS422 LVDS P 2 Xilinx OR RS422 LVDS OR RS422 MAPLD 2009 Gordonicus LLC 17 Development & Debug Ports LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) LEON and Xilinx Ethernet ports can be connected LEON Dedicated Debug Port (DSU) Xilinx I/O to be used as serial ports Xilinx JTAG LEON JTAG ACTEL JTAG
All Debug / Development ports are accessible from the front panel. Facilitates Hardware Reuse GSE reconfiguration without opening the box MAPLD 2009 Gordonicus LLC 18 RTAX 2000 CONFIGURATIONS CG624 Package Supports ALDEC RTAX development Suite. Flexible architecture using Gaisler/ Aeroflex Cores MAPLD 2009 Gordonicus LLC 19 Front Panel & Backplane LVDS / RS 422 Front Panel Transceivers 512 MB SDRAM 256Mx16 Xilinx1a 39 Backplane I /O (P2) 8 RX 8 TX Xilinx1b
512 MB SDRAM 256Mx16 512 MB SDRAM 256Mx16 512 MB Xilinx2a Xilinx2b SDRAM 256Mx16 SelectMAP Space Wire Space Wire 1GB_ EDAC SDRAM 256Mx48 2MB_ EDAC SRAM 32K ROM 23Kx8 ACTEL RTAX 2000 CG624 LEON _3FT
66MHz 4 GByte FLASH 4 GByte FLASH (Front Panel) (2 Backplane) Port SpW Router SpaceWire RS 422 Inputs (Front Panel) Debug Serial Port & JTAG Addr 5 (Front Panel) RS 422 Console Port Data 5 RS 422 Outputs Port SpW Router Ethernet MII 1553 Transformer
Child Abuse and Neglect. CPS Reporting Procedures. Any person making a report to DFPS is immune from civil or criminal liability as long as the report is made in good faith. The reporter's name is confidential. Call the Texas abuse...
Johann Gregor Mendel The Father of Genetics Early Life Born July 22, 1822 In Heinzendorf, Austrian Silesia Now Hyncice, Czech Republic Cobbler's son Many siblings Bright child His Training Entered Augustinian monastery in 1843 Brunn (Brno), Austria Classically trained for...
It is widely accepted in the safety field that unsafe acts contribute/cause 80 - 90% of the incidents in the workplace. Tips from the safety auditors: Safety inspections should be performed more often (weekly) in areas that experience incidents. This...
The PSC's new policy framework provides an opportunity to fundamentally improve the Government of Canada's approach to recruiting Canadians for public service jobs. GCJobs was built on the basis of the previous policy framework, with an overriding emphasis on standardization...
Vaccines Targeting MM Ag Specific Peptides to Delay Progression of Smoldering to Active MM. Using . cocktails of immunogenic . HLA-A2-specific XBP1, CD138, CS1 peptides to induce MM-specific and HLA-restricted CTL responses against several MM antigens
Jane Schaffer "If I can think it, then I can say it. If I can say it, then I can write it!" —J. Schaffer. The Hamburger. Color Coding for Prewriting and Rough Drafts. Topic Sentence - TS (BLUE) Concrete Detail...
* Experiência Joachim Hammerling (1930) Rizóide ou base onde se localiza o núcleo permite a fixação da alga às rochas Caulóide - prolongamento citoplasmático Chapéu - onde se encontram a maioria dos cloroplastos. O núcleo deve ser a estrutura da...
Ready to download the document? Go ahead and hit continue!