Welcome to the ECE 449 Computer Design Lab

Welcome to the ECE 449 Computer Design Lab

ECE 448 Lecture 14 Overview of Modern FPGAs ECE 448 FPGA and ASIC Design with VHDL George Mason University Resources Clive Max Maxfield, The Design Warriors Guide to FPGAs, Elsevier, 2004. ECE 448 FPGA and ASIC Design with VHDL

2 Resources Xcell Journal available for FREE on line @ http://www.xilinx.com/publications/xcellonline/ Electronic Engineering Journal available for FREE by e-mail after subscribing @ http://www.eejournal.com/subscribe or on the web @ http://www.eejournal.com/design/fpga ECE 448 FPGA and ASIC Design with VHDL 3

FPGA Vendors & Families ECE 448 FPGA and ASIC Design with VHDL 4 Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Share about 90% of the market Altera Corp. Atmel Lattice Semiconductor

Flash & antifuse FPGAs Actel Corp. Quick Logic Corp. 5 Xilinx FPGA Families Old families XC3000, XC4000, XC5200 Old 0.5m, 0.35m and 0.25m technology. Not recommended for modern

designs. High-performance families Virtex (220 nm) Virtex-E, Virtex-EM (180 nm) Virtex-II (130 nm) Virtex-II PRO (130 nm) Virtex-4 (90 nm) Virtex-5 (65 nm) Virtex-6 (40 nm) Low Cost Family Spartan/XL derived from XC4000 Spartan-II derived from Virtex Spartan-IIE derived from Virtex-E Spartan-3 (90 nm) Spartan-3E (90 nm) logic optimized

Spartan-3A (90 nm) I/O optimized Spartan-3AN (90 nm) non-volatile, Spartan-3A DSP (90 nm) DSP optimized Spartan-6 (45 nm) ECE 448 FPGA and ASIC Design with VHDL 6 Xilinx FPGA Devices Technology Low-cost 120/150 nm

90 nm Virtex 2, 2 Pro Spartan 3 65 nm 45 nm 40 nm Highperformance Virtex 4 Virtex 5 Spartan 6

Virtex 6 Altera FPGA Devices Technology Low-cost Mid-range Highperformanc e 130 nm Cyclone

Stratix 90 nm Cyclone II Stratix II 65 nm Cyclone III Arria I

Stratix III 40 nm Cyclone IV Arria II Stratix IV LUTs & ALUTs ECE 448 FPGA and ASIC Design with VHDL 4-bit LUTs vs. 6-bit LUTs

6-bit LUTs introduced in Virtex 5 ECE 448 FPGA and ASIC Design with VHDL 10 Major Differences between Xilinx Families Look-Up Tables Spartan 3 Virtex 4 Virtex 5, Virtex 6, Spartan 6

4-input 6-input Number of CLB slices per CLB 4 2 Number of LUTs per CLB slice

2 4 11 Major Differences between Xilinx Families Spartan 3 Virtex 4 Maximum Single-Port Memory Size per LUT 16 x 1 Maximum Shift Register

Size per LUT 16 bits Number of adder stages per CLB slice 2 Virtex 5, Virtex 6, Spartan 6 64 x 1 32 bits 4

12 Altera Cyclone III Logic Element (LE) Normal Mode Altera Stratix III Adaptive Logic Modules (ALM) Normal Mode 14 FPGA Embedded Resources ECE 448 FPGA and ASIC Design with VHDL

Embedded Multipliers ECE 448 FPGA and ASIC Design with VHDL Multipliers in Spartan 3 RAM blocks Multipliers Logic blocks The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 FPGA and ASIC Design with VHDL

18 Number of Multipliers per Spartan 3 Device 19 Combinational and Registered Multiplier ECE 448 FPGA and ASIC Design with VHDL 20 Dedicated Multiplier Block

ECE 448 FPGA and ASIC Design with VHDL 21 Cyclone II Embedded Multiplier Block Overview Each Cyclone II has one to three columns of embedded multipliers. Each embedded multiplier can be configured to support One 18 x 18 multiplier

Two 9 x 9 multipliers Number of Embedded Multipliers Multiplier Block Architecture Two Multiplier Types Two 9x9 multiplier 18x18 multiplier Multiplier Stage Signals signa and signb are used to identify the signed and unsigned inputs.

3 Ways to Use Dedicated Hardware Three (3) ways to use dedicated (embedded) hardware Inference Instantiation CoreGen in Xilinx MegaWizard Plug-In Manager in Altera 28 DSP Units ECE 448 FPGA and ASIC Design with VHDL

Xilinx XtremeDSP Starting with Virtex 4 family, Xilinx introduced DSP48 block for high-speed DSP on FPGAs Essentially a multiply-accumulate core with many other features Now also in Spartan-3A, Spartan 6, Virtex 5, and Virtex 6 30 Multiplier-Accumulator - MAC Multiplier Adder Accumulator A[n:0]

x B[n:0] + MAC Y[(2n - 1):0] The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 31

Mathematical Functions DSP 48 can perform mathematical functions such as: Add/Subtract Accumulate Multiply

Multiply-Accumulate Multiplexer Barrel Shifter Counter Divide (multi-cycle) Square Root (multi-cycle) Can also create filters such as: Serial FIR Filter (Xilinx calls this MACC filters) Parallel FIR Filter

Semi-Parallel FIR Filter Multi-rate FIR Filters 32 DSP48 Slice: Virtex 4 33 Simplified Form of DSP48 Adder Out = (Z (X + Y + CIN)) 34 Choosing Inputs to DSP Adder

P = Adder Out = (Z (X + Y + CIN)) 35 DSP48E Slice : Virtex5 36 New in Virtex 5 Compared to Virtex 4 37 Xilinx DSP48

38 Stratix III DSP Unit Embedded Memories ECE 448 FPGA and ASIC Design with VHDL Memory Types Memory RAM ROM

Memory Single port Dual port Memory With asynchronous read With synchronous read 41 Memory Types in Xilinx

Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Memory Inferred Instantiated Manually Using Core Generator

42 Memory Types in Altera Memory Distributed (ALUT-based, Stratix III onwards) Memory block-based Small size (512) Medium size Large size (4K, 9K, 20K) (144K, 512K)

Memory Inferred Instantiated Manually Using MegaWizard Plug-In Manager 43 Cyclone II Memory Blocks The embedded memory structure consists of columns of M4K memory blocks that can be configured as RAM, first-in first-out (FIFO) buffers, and ROM

Memory Modes The M4K memory blocks support the following modes: Single-port RAM (RAM:1-Port) Simple dual-port RAM (RAM: 2-Port) True dual-port RAM (RAM:2-Port) Tri-port RAM (RAM:3-Port) Single-port ROM (ROM:1-Port)

Dual-port ROM (ROM:2-Port) Single-Port ROM The address lines of the ROM are registered The outputs can be registered or unregistered A .mif file is used to initialize the ROM contents Stratix II TriMatrix Memory Stratix II TriMatrix Memory Stratix III & Stratix IV TriMatrix Memory Stratix II & III Shift-Register Memory Configuration

Supply Voltage ECE 448 FPGA and ASIC Design with VHDL 51 Change in Supply Voltages Year 1998 1999 2000 2001 2003 2008

2009 Technology (nm) 350 250 180 150 130 65 40 ECE 448 FPGA and ASIC Design with VHDL Core Supply Voltage (V) 3.3

2.5 1.8 1.5 1.2 1.0 0.9 52 Gigabit Transceivers ECE 448 FPGA and ASIC Design with VHDL 53

Using a Bus to Communicate Between Devices n-bit bus FPGA Other device The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 54 Using High-Speed Tranceivers to

Communicate Between Devices Transceiver block Differential pairs FPGA The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 FPGA and ASIC Design with VHDL 55 Using High-Speed Tranceivers to

Communicate Between Devices Transceiver block FPGA Transmit (TX) to other device Receive (RX) from other device Differential pairs The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 56

Effect of Noise on Single Wire and Differential Pair Noise spikes (a) (b) 1 IN Outside World FPGA

IN Standard Input RXN Differential Pair 0 Noise spikes RXN 1

RXP 0 RXP The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 57 Generating a Differential Pair Transmitting Device Outside

World TXN TXP The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 58 Multiple Standards for High-Speed Serial Communication Fibre Channel InfiniBand PCI Express (developed by Intel)

RapidIO SkyRail (developed by MindSpeed Technologies) 10-gigabit Ethernet The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 59 Using FPGA to Interface Between Multiple Standards Gigibit interface standard A

Transceiver blocks Gigibit interface standard B Stuff Chip A FPGA Chip B The Design Warriors Guide to FPGAs

Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 60 Ganging Multiple Transceivers Together Four gigabit transceiver blocks 4x electrical differential signal TX and RX pairs at 2.5 gigabits/second each Channel bonding

control signals To/from the main FPGA fabric FPGA Optical cable/signal (10 gigabits/second) The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

61 An Ideal Signal vs. Signal Seen by Receiver 1 0 1 0 1 0

1 0 1 Signal sent from transmitter Signal seen by receiver The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

62 The Effects of Transmitting a Series of Identical Bits 1 1 1 0 1

0 1 0 1 Signal sent from transmitter Signal seen by receiver The Design Warriors Guide to FPGAs

Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 63 Main Elements of the Transceiver Block 8b/10b Encoder FIFO Polarity flipper Serializer

TXP 8-bit bus from main FPGA fabric TXN This is where pre-emphasis takes place Transmitter FIFO

8b/10b Deccoder Polarity flipper Deserializer This is where equalization takes place RXP 8-bit bus to main

FPGA fabric To another device RXN From another device Receiver Transceiver Block

FPGA The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 64 Recovering Clock Signal 1 0 1

0 1 0 1 0 1 0 1

0 (a) Simple signal Real edges 1 1 1 0 0

0 1 0 1 1 0 1 (b) More complex signal

Derived edges Real edges 65 Sampling the Incoming Signal Data sample times Derived edges Real edges 66 Embedded Microprocessors

ECE 448 FPGA and ASIC Design with VHDL 67 Embedded Microprocessor Cores uP uP uP uP

uP (a) One embedded core (b) Four embedded cores The Design Warriors Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 FPGA and ASIC Design with VHDL 68 Virtex-II Pro Architecture 2

3 Features: 1. 2. 3. 4. 5. 6. Processor Block RocketIO Multi-Gigabit Transceivers CLB and Configurable Logic

SelectIO-Ultra Digital Clock Managers Multipliers and Block SelectRAM 1 6 4 ECE 448 FPGA and ASIC Design with VHDL 5

69 ECE 448 FPGA and ASIC Design with VHDL 70 PowerPC Cores PowerPC System PowerPC System ECE 448 FPGA and ASIC Design with VHDL

71 Embedded Development Kit (EDK) Software Flow Hardware Flow Processor IP, Microprocessor Peripheral Description Files VHDL / Verilog

C / C++ Code Libraries PlatGen Synthesizer Compiler LibGen Microprocessor Hardware Specification

File EDIF IP Netlists Object Files Microprocessor Software Specification File ISE / Xflow Linker

System Constraint File Bitstream Data2MEM Executable Download to FPGA ECE 448 FPGA and ASIC Design with VHDL

72

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